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参数资料
| 型号： | MC68838FCC |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 1 CHANNEL(S), 125M bps, FDDI CONTROLLER, CQFP120 |
| 封装： | CERAMIC, QFP-120 |
| 文件页数： | 9/100页 |
| 文件大小： | 465K |
| 代理商： | MC68838FCC |
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2-4
MC68838 USER’S MANUAL
MOTOROLA
2.2.6 Address Comparator
This block performs part of the DA actions, SA actions, and CT actions as specified in the
FDDI MAC standard. Specifically, this block compares the DA and SA fields of received
frames to this station's individual addresses (my short address register and my long
address register). It also compares the INFO field of received claim frames (the token
rotation time requested by another station) to this station's desired token rotation time.
This logic block has two parts:
1. A register array that contains this station's individual 16- and 48-bit address (my
short address register and my long address register) and this station's desired
token rotation time. This register block contains a byte-wide read-only port that
feeds into the comparator and into the transmit data path when generating claim,
beacon, and void frames.
2. The comparison logic part that contains a byte-wide comparator that gets its inputs
from the register array and from the receive data path).
The receive FSM controls this logic, and the results of the comparison are passed to the
receive FSM.
2.2.7 Receive Host Interface
The FSI receive logic controls the RPATHx bus and RCCTLx bus that pass received
frames to the FSI. lt strips off the delimiters before passing the frame to the FSI. lt
handles all the extra control and handshake lines required for the RPATHx bus. The
receive FSM controls this logic and receives abort/flush signals from it. The system
interface receive logic is completely separate from, and does not communicate with, the
system interface transmit logic.
2.3 TRANSMIT DATA PATH
The transmit data path is the internal data path associated with the transmission of data
onto the ring. The send frame logic assembles a packet consisting of preamble (idles),
JK, FC, DA, SA, INFO field, CRC, T, and the FS indicators from various sources.
Frame_Data is multiplexed with either idles or repeat data from the receive data path in
the transmit latch logic. The transmit latch logic contains the TXDATx pipeline latch that
drives the TXDATx external bus. The TXDATx external bus passes a symbol pair to the
ELM chip on the following BYTCLK cycle after the MAC chip has received it.
ARCHIVE
INFORMA
TION
ARCHIVE
INFORMA
TION
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