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| 型号： | MC68HC05BS8FB |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 2.2 MHz, MICROCONTROLLER, PQFP44 |
| 封装： | PLASTIC, QFP-44 |
| 文件页数： | 109/128页 |
| 文件大小： | 9691K |
| 代理商： | MC68HC05BS8FB |
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MC68HC05BS8
SYNC SIGNAL PROCESSOR
9
9.6
Vertical Sync Pulse Reshaper
The vertical sync pulse width at VTTL output is formatted by the Vertical Sync Pulse Reshaper,
such that, it’s falling edge follows the input signal’s falling edge, and it’s rising edge is at the 6th
falling edge of the input horizontal sync signal (HSYNC). Notice that, if the input signal is a
composite signal, the VTTL pulse width will be longer, for there may not be any falling edge during
the vertical sync pulse period. Figure 9-3 shows the different in VTTL pulse widths for different
input signal formats.
9.7
Sync Signal Counters
There are two counters (horizontal line counter and vertical frequency counter) to count the
number of horizontal sync pulses and the number of system clock cycles between two vertical
sync pulses. These two data can be read by the CPU to check the signal frequencies and can be
used to determine the video mode. Notice that the value in the vertical frequency counter will be
subtracted by 240 before loading into the Vertical Frequency register. In this way, the 9-bit register
can cover a vertical frequency ranged from 42Hz to 130Hz. Figure 9-4 shows a more detailed
block diagram of these counters. Figure 9-4 shows the vertical frequency counter timings. It
indicates that there will be
±1 count error on the reading from the register for the same vertical
frequency.
Figure 9-3 VTTL Pulse Widths For Different Input Signal Formats
123456
123
456
123456
VSYNC
HSYNC
Re-shaped
VTTL output
Re-shaped
VTTL output
Re-shaped
VTTL output
CSYNC with H pulses
during V pulse period
CSYNC without H pulses
during V pulse period
TPG
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For More Information On This Product,
Go to: www.freescale.com
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