- 您现在的位置：买卖IC网 > PDF目录69028 > MC68HC05BS8FB (FREESCALE SEMICONDUCTOR INC) 8-BIT, MROM, 2.2 MHz, MICROCONTROLLER, PQFP44 PDF资料下载
参数资料
| 型号： | MC68HC05BS8FB |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 2.2 MHz, MICROCONTROLLER, PQFP44 |
| 封装： | PLASTIC, QFP-44 |
| 文件页数： | 91/128页 |
| 文件大小： | 9691K |
| 代理商： | MC68HC05BS8FB |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页当前第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页
MC68HC05BS8
M-BUS SERIAL INTERFACE
8
generate a STOP condition. Meanwhile, a software bit will be set by hardware to indicate loss of
arbitration.
8.2.7
Clock Synchronization
Since wire-AND logic is performed on the SCL line, a high to low transition on SCL line will affect
the devices connected to the bus. The devices start counting their low period and once a device's
clock has gone low, it will hold the SCL line low until the clock high state is reached. However, the
change of low to high in this device clock may not change the state of the SCL line, if another
device clock is still in its low period. Therefore synchronized clock SCL will be held low by the
device which releases SCL to a logic high in the last place. Devices with shorter low periods enter
a high wait state during this time (see Figure 8-3). When all devices concerned have counted off
their low period, the synchronized clock SCL line will be released and go high. All of them will start
counting their high periods. The rst device to complete its high period will again pull the SCL line
low.
8.2.8
Handshaking
The clock synchronization mechanism can be used as a handshake in data transfer. Slave device
may hold the SCL low after completion of one byte transfer (9 bits). In such case, it will halt the
bus clock and force the master clock in a wait state until the slave releases the SCL line.
Figure 8-3 Clock Synchronization
SCL1
SCL2
SCL
Internal counter reset
WAIT
Start counting high period
TPG
63
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
..
.
相关PDF资料 |
PDF描述 |
|---|---|
| MC68HC705C9CFN | 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PQCC44 |
| MC68HC705C9FN | 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PQCC44 |
| MC68HC705C9P | 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PDIP40 |
| MC68HC705E5DW | 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDSO28 |
| MC68HC705G1B | 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDIP56 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MC68HC05C0CP | 制造商:Motorola Inc 功能描述: |
| MC68HC05C12 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:HCMOS MICROCONTROLLER UNITS |
| MC68HC05C12B | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:HCMOS MICROCONTROLLER UNITS |
| MC68HC05C12CP | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:HCMOS MICROCONTROLLER UNITS |
| MC68HC05C12P | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:HCMOS MICROCONTROLLER UNITS |
发布紧急采购，3分钟左右您将得到回复。