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参数资料
| 型号： | MC68HC05RC9P |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP28 |
| 封装： | PLASTIC, DIP-28 |
| 文件页数： | 60/124页 |
| 文件大小： | 457K |
| 代理商： | MC68HC05RC9P |
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NON-DISCLOSURE
AGREEMENT
REQUIRED
Interrupts
General Release Specification
MC68HC05RC18 — Rev. 2.0
40
Interrupts
MOTOROLA
4.3 CPU Interrupt Processing
Interrupts cause the processor to save register contents on the stack
and to set the interrupt mask (I bit) to prevent additional interrupts. Unlike
reset, hardware interrupts do not cause the current instruction execution
to be halted, but are considered pending until the current instruction is
complete.
If interrupts are not masked (I bit in the CCR is clear) when the CPU
receives an interrupt request, the processor will proceed with interrupt
processing. Otherwise, the next instruction is fetched and executed. If an
interrupt occurs, the processor completes the current instruction, stacks
the current CPU register state, sets the I bit to inhibit further interrupts,
and finally checks the pending hardware interrupts. If more than one
interrupt is pending after the stacking operation, the interrupt with the
highest vector location shown in Table 4-1 will be serviced first. The SWI
is executed the same as any other instruction, regardless of the I-bit
state.
When an interrupt is to be processed, the CPU fetches the address of
the appropriate interrupt software service routine from the vector table at
locations $3FF6–$3FFF as defined in Table 4-1.
The M68HC05 CPU does not support interruptible instructions. The
maximum latency to the first instruction of the interrupt service routine
must include the longest instruction execution time plus stacking
overhead.
Latency = (Longest instruction execution time + 10) x tcyc seconds
An RTI instruction is used to signify when the interrupt software service
routine is completed. The RTI instruction causes the register contents to
be recovered from the stack and normal processing to resume at the
next instruction that was to be executed when the interrupt took place.
Figure 4-1 shows the sequence of events that occurs during interrupt
processing.
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