- 您现在的位置：买卖IC网 > PDF目录80448 > MC68HC05RC9P (MOTOROLA INC) 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP28 PDF资料下载
参数资料
| 型号： | MC68HC05RC9P |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP28 |
| 封装： | PLASTIC, DIP-28 |
| 文件页数： | 99/124页 |
| 文件大小： | 457K |
| 代理商： | MC68HC05RC9P |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页当前第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页
NON-DISCLOSURE
AGREEMENT
REQUIRED
Carrier Modulator Transmitter (CMT)
General Release Specification
MC68HC05RC18 — Rev. 2.0
76
Carrier Modulator Transmitter (CMT)
MOTOROLA
IROLN and IROLP — IRO Latch Control
Reading IROLN or IROLP reads the state of the IRO latch. Writing
IROLN updates the IRO latch with the data being written on the
negative edge of the internal processor clock (fosc/2). Writing IROLP
updates the IRO latch on the positive edge of the internal processor
clock; for example, one fosc period later. The IRO latch is clear out of
reset.
NOTE:
Writing to CHR1 to update IROLN or to CLR1 to update IROLP will also
update the primary carrier high and low data values. Care should be
taken that bits 5–0 of the data to be written to CHR1 or CHL1 should
contain the desired values for the primary carrier high or low data.
In addition, writing to CHR1 to update IROLN will update the CMT
polarity bit. Care should be taken that bit 6 of the data to be written to
CHR1 should contain the desired values for the polarity bit.
9.5 Modulator
The modulator consists of a 12-bit down counter with underflow
detection which is loaded from the modulation mark period from the
mark buffer register, MBUFF. When this counter underflows, the
modulator gate is closed and a 12-bit comparator is enabled which
continually compares the logical complement of the contents of the (still)
decrementing counter with the contents of the modulation space period
register, SREG. When a match is obtained, the modulator control gate
is opened again. Should SREG = 0, the match will be immediate and no
space period will be generated (for instance, for FSK protocols which
require successive bursts of different frequencies). When the match
occurs, the counter is reloaded with the contents of MBUFF, SREG is
reloaded with the contents of its buffer, SBUFF, and the cycle repeats.
The MCGEN bit in the MCSR must be set to enable the modulator timer.
The 12-bit MBUFF and SBUFF registers are accessed through three 8-
bit modulator period registers, MDR1, MDR2, and MDR3.
The modulator can operate in two modes, time and FSK. In time mode,
the modulator counts clocks derived from the system oscillator and
相关PDF资料 |
PDF描述 |
|---|---|
| MC68008L12D | 16-BIT, 12.5 MHz, MICROPROCESSOR, CDIP48 |
| MDDFMM-TTL-16J | 16 MHz, OTHER CLOCK GENERATOR, PDSO4 |
| MDDFMM-TTL-2F | 2 MHz, OTHER CLOCK GENERATOR, PDIP4 |
| MC68010P12F | 32-BIT, 16.67 MHz, MICROPROCESSOR, PDIP64 |
| MC68EC000FU12F | 32-BIT, 16.67 MHz, MICROPROCESSOR, PQFP64 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MC68HC05SC24 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:Secure 8-bit microcomputer with EEPROM |
| MC68HC05SR3 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller Units |
| MC68HC05SU3A | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Fully static chip design featuring the industry standard 8-bit M68HC05 core |
| MC68HC05T16 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit |
| MC68HC05V12 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:HCMOS Microcontreller Unit |
发布紧急采购，3分钟左右您将得到回复。