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参数资料
| 型号： | MC68HC05SR3CB |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PDIP42 |
| 封装： | SDIP-42 |
| 文件页数： | 64/96页 |
| 文件大小： | 612K |
| 代理商： | MC68HC05SR3CB |
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MC68HC05SR3
MOTOROLA
8-13
CPU CORE AND INSTRUCTION SET
8
8.3.8
Relative
The relative addressing mode is only used in branch instructions. In relative addressing, the
contents of the 8-bit signed byte (the offset) following the opcode are added to the PC if, and only
if, the branch conditions are true. Otherwise, control proceeds to the next instruction. The span of
relative addressing is from –126 to +129 from the opcode address. The programmer need not
calculate the offset when using the Motorola assembler, since it calculates the proper offset and
checks to see that it is within the span of the branch.
EA = PC+2+(PC+1); PC
← EA if branch taken;
otherwise EA = PC
← PC+2
8.3.9
Bit set/clear
In the bit set/clear addressing mode, the bit to be set or cleared is part of the opcode. The byte
following the opcode species the address of the byte in which the specied bit is to be set or
cleared. Any read/write bit in the rst 256 locations of memory, including I/O, can be selectively
set or cleared with a single two-byte instruction.
EA = (PC+1); PC
← PC+2
Address bus high
← 0; Address bus low ← (PC+1)
8.3.10
Bit test and branch
The bit test and branch addressing mode is a combination of direct addressing and relative
addressing. The bit to be tested and its condition (set or clear) is included in the opcode. The
address of the byte to be tested is in the single byte immediately following the opcode byte (EA1).
The signed relative 8-bit offset in the third byte (EA2) is added to the PC if the specied bit is set
or cleared in the specied memory location. This single three-byte instruction allows the program
to branch based on the condition of any readable bit in the rst 256 locations of memory. The span
of branch is from –125 to +130 from the opcode address. The state of the tested bit is also
transferred to the carry bit of the condition code register.
EA1 = (PC+1); PC
← PC+2
Address bus high
← 0; Address bus low ← (PC+1)
EA2 = PC+3+(PC+2); PC
← EA2 if branch taken;
otherwise PC
← PC+3
TPG
65
相关PDF资料 |
PDF描述 |
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| MC68HC05SR3CP | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PDIP40 |
| MC68HC705SR3B | 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PDIP42 |
| MC68HC05SR3FB | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQFP44 |
| MC68HC05SR3P | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PDIP40 |
| MC68HC705SR3CFB | 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PQFP44 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MC68HC05SU3A | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Fully static chip design featuring the industry standard 8-bit M68HC05 core |
| MC68HC05T16 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit |
| MC68HC05V12 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:HCMOS Microcontreller Unit |
| MC68HC05V12CFN | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:General Release Specification |
| MC68HC05X16 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:High-density complementary metal oxide semiconductor HCMOS) microcontroller unit |
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