参数资料
型号: MC68HC05SR3CB
厂商: MOTOROLA INC
元件分类: 微控制器/微处理器
英文描述: 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PDIP42
封装: SDIP-42
文件页数: 87/96页
文件大小: 612K
代理商: MC68HC05SR3CB
MOTOROLA
A-2
MC68HC05SR3
MC68HC705SR3
A
A.2
Modes of Operation
The MC68HC705SR3 has two modes of operation – user mode and EPROM bootstrap mode.
Table A-1 shows the conditions required to enter each mode on the rising edge of RESET.
A.3
User Mode
The normal operating mode of the MC68HC705SR3 is the user mode. User mode will be entered
on the rising edge of RESET when the VPP and PB1 pins are between VSS and VDD.
Warning: In the MC68HC705SR3, all vectors are fetched from EPROM in user mode; therefore,
the EPROM must be programmed (via the bootstrap mode) before the device is
powered up in user mode.
A.4
Bootstrap Mode
The bootstrap mode is provided as a mean of self-programming MC68HC705SR3 EPROM with
minimal circuitry, and can only run in the crystal oscillator mode. Bootstrap mode will be entered
on the rising edge of RESET when the VPP pin is at VTST (2×VDD) and PB1 pin is at VDD. Once in
the bootstrap mode, PB1 can then be used for other purposes. After entering the bootstrap mode,
CPU branches to the bootstrap program and carries out the EPROM programming routine. The
user EPROM consists of 3840 bytes, from location $1000 to $1EFF.
This program handles copying of user code from an external EPROM into the on-chip EPROM.
The bootstrap function does not have to be done from an external EPROM, but it may be done
from a host.
The user code must be a one-to-one correspondence with the internal EPROM addresses.
Table A-1 MC68HC705SR3 Operating Mode Entry Conditions
RESET
VPP
PB1
MODE
VSS to VDD
USER
VTST
VDD
BOOTSTRAP
VTST=2×VDD
5V
TPG
86
相关PDF资料
PDF描述
MC68HC05SR3CP 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PDIP40
MC68HC705SR3B 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PDIP42
MC68HC05SR3FB 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQFP44
MC68HC05SR3P 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PDIP40
MC68HC705SR3CFB 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PQFP44
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