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参数资料
| 型号： | MC68HC08AS20CFN |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, MICROCONTROLLER, PQCC52 |
| 封装： | PLASTIC, LCC-52 |
| 文件页数： | 35/96页 |
| 文件大小： | 3243K |
| 代理商： | MC68HC08AS20CFN |
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4
MOTOROLA
4-4
MC68HC05E0
RESETS, INTERRUPTS AND LOW POWER MODES
Table 4-1 shows the relative priority of all the possible interrupt sources. Internally, the External
Interrupt, Real Time Interrupt, and Wake-up signals are “ORed” to generate the CPU interrupt
signal IRQB. The source responsible for generating the IRQB interrupt can be determined by
examining the interrupt ag bits associated with these sources.
Note:
The external interrupt INTX can be disabled by setting the External Interrupt Mask bit
(INTMX) in the Interrupt Control Register ($000E).
For example, if both an external interrupt and a Timer A interrupt are pending at the end of an
instruction execution, the external interrupt is serviced rst.
The software interrupt SWI is executed in the same way as any other instruction, regardless of the
state of the I-bit.
4.2.1
Hardware Controlled Interrupt Sequence
The following three functions (RESET, STOP, and WAIT) are not in the strictest sense interrupts.
However, they are acted upon in a similar manner. Flowcharts for hardware interrupts are shown
in Figure 4-3, and for STOP and WAIT in Figure 4-4.
RESET:
A reset condition causes the program to vector to its starting address which is specied
by the contents of memory locations $FFFE (MSB) and $FFFF (LSB). The I bit in the
condition code register is also set.
STOP:
The STOP instruction causes the oscillator to be turned off and the processor to “sleep”
until an external interrupt (INTX) (if enabled), a wake-up interrupt (if enabled) or reset
occurs.
WAIT:
The WAIT instruction causes all processor clocks to stop, but leaves the timer clock
running. This “rest” state of the processor can be cleared by reset, an external interrupt
(INTX) (if enabled), a wake-up interrupt or a Timer/SI interrupt. There are no special
wait vectors for these individual interrupts.
Table 4-1 Interrupt Priorities
Source
Vector address
Priority
Real time interrupt
$FFFA, $FFFB
highest
External interrupt (INTX)
Wake-up (Port C)
Timer A
$FFF8, $FFF9
Timer B
$FFF6, $FFF7
Serial interface
$FFF4, $FFF5
lowest
40
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