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| 型号： | MC68HC11A0CP3 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PDIP48 |
| 封装： | PLASTIC, DIP-48 |
| 文件页数： | 120/158页 |
| 文件大小： | 3803K |
| 代理商： | MC68HC11A0CP3 |
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SERIAL PERIPHERAL INTERFACE
MC68HC11A8
6-6
TECHNICAL DATA
6
WCOL — Write Collision
The write collision bit is set when an attempt is made to write to the serial peripheral
data register while data transfer is taking place. If CPHA is zero a transfer is said to
begin when SS goes low and the transfer ends when SS goes high after eight clock
cycles on SCK. When CPHA is one a transfer is said to begin the first time SCK be-
comes active while SS is low and the transfer ends when the SPIF flag gets set. Clear-
ing the WCOL bit is accomplished by reading the SPSR (with WCOL set) followed by
an access to SPDR.
Bit 5 — Not Implemented
This bit always reads zero.
MODF — Mode Fault
The mode fault flag indicates that there may have been a multi-master conflict for sys-
tem control and allows a proper exit from system operation to a reset or default system
state. The MODF bit is normally clear, and is set only when the master device has its
SS pin pulled low. Setting the MODF bit affects the internal serial peripheral interface
system in the following ways:
1. An SPI interrupt is generated if SPIE = 1.
2. The SPE bit is cleared. This disables the SPI.
3. The MSTR bit is cleared, thus forcing the device into the slave mode.
4. DDRD bits for the four SPI pins are forced to zeros.
Clearing the MODF bit is accomplished by reading the SPSR (with MODF set), fol-
lowed by a write to the SPCR. Control bits SPE and MSTR may be restored by user
software to their original state after the MODF bit has been cleared. It is also neces-
sary to restore DDRD after a mode fault.
Bits 3-0 — Not Implemented
These bits always read zero.
6.4.3 Serial Peripheral Data l/O Register (SPDR)
The serial peripheral data l/O register is used to transmit and receive data on the serial
bus. Only a write to this register will initiate transmission/reception of another byte, and
this will only occur in the master device. At the completion of transmitting a byte of da-
ta, the SPIF status bit is set in both the master and slave devices.
When the user reads the serial peripheral data l/O register, a buffer is actually being
read. The first SPIF must be cleared by the time a second transfer of data from the
shift register to the read buffer is initiated or an overrun condition will exist. In cases of
overrun the byte which causes the overrun is lost.
A write to the serial peripheral data l/O register is not buffered and places data directly
into the shift register for transmission.
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For More Information On This Product,
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