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参数资料
| 型号： | MC68HC11C0MFN2 |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, 2 MHz, MICROCONTROLLER, PQCC68 |
| 封装： | PLASTIC, LCC-68 |
| 文件页数： | 15/76页 |
| 文件大小： | 394K |
| 代理商： | MC68HC11C0MFN2 |
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MOTOROLA
MC68HC11C0
22
MC68HC11C0TS/D
4.2 Chip Selects
Seven chip select signals are provided to simplify the interface to external components. Five general-
purpose and one program/vector chip select pin are implemented as alternate functions of port G pins.
Port G pull-ups are enabled out of reset in order to provide a logic level one on all chip select and mem-
ory expansion address lines. The chip selects are designed to operate with or without memory expan-
sion. All chip selects are prioritized so that they never conflict with each other or with on-chip resources.
General-purpose chip selects are automatically activated (if enabled) whenever the current CPU ad-
dress falls within a range defined by the associated control registers for each chip select. All general-
purpose chip selects use the same format for selecting starting address, ending address, and clock
stretch. Each of the five general-purpose chip selects has two control registers associated with it. The
first register (GPxSADR) selects the upper six MSB of the starting address and selects the clock stretch.
The second register (GPxEADR) selects the upper six MSB of the ending address. Since these bits are
the upper six MSB, the granularity of each chip select range is 1024bytes. Each general-purpose chip
select is an active-low signal with a programmable clock stretch from zero to three E-clock cycles. Bits
in the PGEN register enable each of the five general-purpose chip selects. When a chip select is en-
abled, the corresponding port G pin is forced to be an output regardless of the state of the DDGx bit.
The program chip select (CSPROG) simplifies the interface to external devices and functions with or
without memory expansion. CPU address lines ADDR[15:10] are always used to decode the program
chip select; therefore, its granularity is fixed at 1 Kbyte. The range is defined by bits in PGSADR and
PGEADR. When the CPU address falls within the defined range, CSPROG is asserted. If memory ex-
pansion is enabled, the range of the program chip select corresponds to the memory expansion win-
dow. In this case, CSPROG will be asserted and the current CPU address will become modified
according to the contents of the memory expansion address registers MXHADR and MXLADR before
being driven out to the external device. Refer to 4.1 Memory Expansion for more information.
The vector chip select (CSV) is provided for the vector space and, because there is no internal memory
at the reset vector address, is enabled for the entire address space out of reset in expanded mode. VC-
SADR selects the upper six MSB of the starting address. Since these bits are the upper six MSB, the
granularity of the vector chip select range is 1024 bytes. The ending address is the highest address
($FFFF). The vector chip select is an active-low signal with a programmable clock stretch from zero to
three E-clock cycles. Bits in the PGEN register enable each of the five general-purpose chip selects.
Whenever the CPU logical address falls within the range defined by VCSADR, CSV is asserted and the
current CPU logical address is driven out ADDR[15:0] to the external memory device. XA[17:16] (if en-
abled) are always driven high when vector space is selected to ensure that the vector space is always
located at the top of the address space. CSV is configured for one cycle of clock stretch out of reset in
expanded mode. This can be altered by changing the values in PSTHA and PSTHB in PGSADR regis-
ter. When CSV is enabled, PG0 is forced to be an output regardless of the state of the DDG0 bit.
CAUTION
If program code is contained in an external memory, the range for CSPROG must
be defined before the vector chip select range is changed. This prevents the pro-
gram from being lost at the point when CSV is changed.
The range of the program chip select is defined as follows:
PSA[15:10]
≤ADDR[15:10] < PEA[15:10]
The range of the vector chip select is defined as follows:
VSA[15:10]
≤ADDR[15:10] ≤$3FFF
where,
PSA = bits in PGSADR register
PEA = bits in PGEADR register
VSA = bits in VCSADR register
ADDR = CPU logical address
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相关代理商/技术参数 |
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| MC68HC11C0MFU2 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:8-Bit Microcontroller |
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| MC68HC11C0VFU2 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:8-Bit Microcontroller |
| MC68HC11D0 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Microcontrollers |
| MC68HC11D0CFB2 | 制造商:Rochester Electronics LLC 功能描述:8BIT MCU,192 BYTES RAM - Bulk 制造商:Freescale Semiconductor 功能描述: 制造商:Motorola Inc 功能描述: 制造商:MOTOROLA 功能描述: |
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