参数资料
型号: MC68HC11C0MFN2
厂商: MOTOROLA INC
元件分类: 微控制器/微处理器
英文描述: 8-BIT, 2 MHz, MICROCONTROLLER, PQCC68
封装: PLASTIC, LCC-68
文件页数: 51/76页
文件大小: 394K
代理商: MC68HC11C0MFN2
MC68HC11C0
MOTOROLA
MC68HC11C0TS/D
55
PPOL[2:1] — Pulse-Width Channel x Polarity
0 = PWM channel x output is low at the beginning of the clock cycle and goes high when duty count
is reached
1 = PWM channel x output is high at the beginning of the clock cycle and goes low when duty count
is reached
Scaled clock S is generated by dividing clock A by the value in PWSCAL, then dividing the result by 2.
If PWSCAL = $00, divide clock A by 256, then divide the result by 2.
TPWSL — PWM Scaled Clock Test Bit (TEST)
DISCP — Disable Compare Scaled E Clock (TEST)
Bits [5:2] — Not implemented
Always read zero
PWEN[2:1] — Pulse-Width Channel 1–2
0 = Channel disabled
1 = Channel enabled
PWCNT1–PWCNT2
Begins count using the selected clock. A write to PWCNTx registers causes them to reset to $00.
PWPER1–PWPER2
Determines period of associated PWM channel
Period registers can be written any time. A new value written to a period register does not take effect
until the counter resets and the new value is latched. Users may begin the new period immediately by
writing the new value to the period register, then writing any value to the counter. The counter will reset
and the new period value will be latched. If the value in the period register is equal to or less than the
value in the duty register, there will be no change in state. Refer to 9.1 PWM Boundary Cases.
PWSCAL — Pulse-Width Modulation Timer Prescaler
$0062
Bit 7
654321
Bit 0
76543210
RESET:
00000000
PWEN — Pulse-Width Modulation Timer Enable
$0063
Bit 7
654321
Bit 0
TPWSL
DISCP
————
PWEN2
PWEN1
RESET:
00000000
TPWCNT1–PWCNT2 — Pulse-Width Modulation Timer Counter 1 to 2 $0066–$0067
$0066
Bit 7
654321
Bit 0
PWCNT1
$0067
Bit 7
654321
Bit 0
PWCNT2
RESET:
00000000
PWPER1–PWPER2 — Pulse-Width Modulation Timer Period 1 to 2
$006A–$006B
$006A
Bit 7
654321
Bit 0
PWPER1
$006B
Bit 7
654321
Bit 0
PWPER2
RESET:
11111111
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