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参数资料
| 型号： | MC68HC11C0MFN2 |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, 2 MHz, MICROCONTROLLER, PQCC68 |
| 封装： | PLASTIC, LCC-68 |
| 文件页数： | 30/76页 |
| 文件大小： | 394K |
| 代理商： | MC68HC11C0MFN2 |
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MOTOROLA
MC68HC11C0
36
MC68HC11C0TS/D
6 Resets and Interrupts
The MC68HC11C0 has three reset vectors and 18 interrupt vectors. The reset vectors are as follows:
RESET, or Power-On Reset
Clock Monitor Fail
COP Failure
The 18 interrupt vectors service 30 interrupt sources (three non-maskable, 27 maskable). The three
non-maskable interrupt vectors are as follows:
XIRQ Pin (X-Bit Interrupt)
Illegal Opcode Trap
Software Interrupt
On-chip peripheral systems generate maskable interrupts, which are recognized only if the global inter-
rupt mask bit (I) in the condition code register (CCR) is clear. Maskable interrupts are prioritized accord-
ing to a default arrangement; however, any one source can be elevated to the highest maskable priority
position by a software-accessible control register, HPRIO. The HPRIO register can be written at any
time, provided the I bit in the CCR is set.
Twenty-seven interrupt sources in the MC68HC11C0 are subject to masking by a global interrupt mask
bit (I bit in the CCR). In addition to the global I bit, all of these sources are controlled by local enable bits
in control registers. Most interrupt sources in M68HC11 devices have separate interrupt vectors; there-
fore, it is not usually necessary for software to poll control registers to determine the cause of an inter-
rupt. In the case of the keyboard interrupt inputs, software must poll the port F interrupt status register
(FISTAT) immediately following an interrupt to determine its source.
For some interrupt sources, such as the SCI and keyboard interrupts, flags are automatically cleared
during the normal course of responding to the interrupt requests. For example, the RDRF flag in the SCI
system is cleared by an automatic clearing mechanism consisting of a read of the SCI status register
while RDRF is set, followed by a read of the SCI data register. The normal response to an RDRF inter-
rupt request would be to read the SCI status register to check for receive errors, then to read the re-
ceived data from the SCI data register. These two steps satisfy the automatic clearing mechanism
without requiring any special instructions. Similarly, port F interrupt status register (FISTAT) is cleared
when the CPU reads the register to determine which input was the source of the interrupt.
Refer to the following table for interrupt and reset vector assignments.
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相关代理商/技术参数 |
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|---|---|
| MC68HC11C0MFU2 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:8-Bit Microcontroller |
| MC68HC11C0VFN2 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:8-Bit Microcontroller |
| MC68HC11C0VFU2 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:8-Bit Microcontroller |
| MC68HC11D0 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Microcontrollers |
| MC68HC11D0CFB2 | 制造商:Rochester Electronics LLC 功能描述:8BIT MCU,192 BYTES RAM - Bulk 制造商:Freescale Semiconductor 功能描述: 制造商:Motorola Inc 功能描述: 制造商:MOTOROLA 功能描述: |
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