参数资料
型号: MC68HC11C0MFN2
厂商: MOTOROLA INC
元件分类: 微控制器/微处理器
英文描述: 8-BIT, 2 MHz, MICROCONTROLLER, PQCC68
封装: PLASTIC, LCC-68
文件页数: 76/76页
文件大小: 394K
代理商: MC68HC11C0MFN2
MC68HC11C0
MOTOROLA
MC68HC11C0TS/D
9
are located in internal RAM at locations $04C4–$04FD. The bootstrap ROM contains a small program
which initializes the SCI and allows the user to download a program of up to 256 bytes into on-chip
RAM. The program must begin at $0400. After an idle time of four-characters, or after receiving the
character for address $04FF, control passes to the loaded program at $0400. Refer to the memory map
diagram.
2.4 Special Test Mode
Special test mode is similar to expanded mode and is used primarily for production testing. The 1024-
byte bootstrap ROM is enabled and present at locations $FC00–$FFFF. In this operating mode, vectors
are fetched from external locations $BFC0–$BFFF.
2.5 Mode Selection
Although it is intended primarily for operation in expanded mode, the MC68HC11C0 has four possible
operating modes. The MC68HC11C0 can be reset to either expanded mode or special-test mode. The
initial operating mode is determined by the logic level present on the MODB pin during reset. After reset,
the operating mode may be changed according to the table contained in the following description of the
HPRIO register.
The function of internal read visibility/not E is determined by the state of the IRVNE bit and the mode
selected. When enabled, internal read visibility (IRV) causes the data from internal reads to be driven
out the data bus. The user must be cautioned that even though the R/W line suggests that the data bus
is in a high-impedance state, data will be driven out each time an internal read occurs. The not E clock
(NE) function of this bit determines whether the E clock is on or off. Refer to the description of IRVNE
in the OPT2 register.
*The reset value of SMOD depends on the logic level present on the MODB pin at the rising edge of reset.
RBOOT — Read Bootstrap ROM
Valid only when SMOD is set (bootstrap or special test mode). Resets to logic one in bootstrap mode
only. Can only be written in special modes.
0 = Bootloader ROM disabled and not in map
1 = Bootloader ROM enabled and in map at $BE00–$BFFF
SMOD and MDA — Special Mode Select and Mode Select A
The initial value of SMOD is the inverse of the logic level present on the MODB pin at the rising edge
of reset. The reset value of MDA is one. The value of MDA determines which operating mode is selected
after reset. These two bits can be read at any time. They can be written anytime in test modes (SMOD
= 1). MDA can only be written once in normal modes. SMOD cannot be set once it has been cleared.
HPRIO — Highest Priority I-Bit Interrupt and Miscellaneous
$003C
Bit 7
654321
Bit 0
RBOOT
SMOD*
MDA
PSEL3
PSEL2
PSEL1
PSEL0
RESET:
0
100101
Logic Level of
MODB Pin at Reset
Value of SMOD
Latched at Reset
Programmed
Value of MDA
Mode Selected
1
0
1
Expanded
0
1
Special Test
1
0
Single Chip
0
1
0
Bootstrap
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