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| 型号： | MC68HC11D0CFBE3 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 66/124页 |
| 文件大小： | 0K |
| 描述： | IC MCU 8BIT 3MHZ 44-QFP |
| 标准包装： | 480 |
| 系列： | HC11 |
| 核心处理器： | HC11 |
| 芯体尺寸： | 8-位 |
| 速度： | 3MHz |
| 连通性： | SCI，SPI |
| 外围设备： | POR，WDT |
| 输入/输出数： | 26 |
| 程序存储器类型： | ROMless |
| RAM 容量： | 192 x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 4.5 V ~ 5.5 V |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 44-QFP |
| 包装： | 托盘 |
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RESETS AND INTERRUPTS
5-2
TECHNICAL DATA
COP is enabled, the software is responsible for keeping a free-running watchdog timer
from timing out. When the software is no longer being executed in the intended se-
quence, a system reset is initiated.
The state of the NOCOP bit in the CONFIG register determines whether the COP sys-
tem is enabled or disabled. In normal modes, COP is enabled out of reset and does
not depend on software action. To disable the COP system, set the NOCOP bit in the
CONFIG register. In the special test and bootstrap operating modes, the COP system
is initially inhibited by the disable resets (DISR) control bit in the TEST1 register. The
DISR bit can subsequently be written to zero to enable COP resets.
The COP timer rate control bits CR[1:0] in the OPTION register determine the COP
time-out period. The system E clock is divided by 215 and then further scaled by a fac-
tor shown in Table 5-1. After reset, these bits are zero, which selects the fastest time-
out period. In normal operating modes, these bits can only be written once within 64
bus cycles after reset.
Complete the following reset sequence to service the COP timer. Write $55 to CO-
PRST to arm the COP timer clearing mechanism. Then write $AA to COPRST to clear
the COP timer. Performing instructions between these two steps is possible as long as
both steps are completed in the correct sequence before the timer times out.
5.1.4 Clock Monitor Reset
The clock monitor circuit is based on an internal RC time delay. If no MCU clock edges
are detected within this RC time delay, the clock monitor can optionally generate a sys-
tem reset. The clock monitor function is enabled or disabled by the CME control bit in
the OPTION register. The presence of a time-out is determined by the RC delay, which
allows the clock monitor to operate without any MCU clocks.
Clock monitor is used as a backup for the COP system. Because the COP needs a
clock to function, it is disabled when the clocks stop. Therefore, the clock monitor sys-
tem can detect clock failures not detected by the COP system.
Table 5-1 COP Time-out
CR[1:0]
Divide
E/215
By
XTAL = 4.0 MHz
Time-out
–0/+32.8 ms
XTAL = 8.0 MHz
Time-out
–0/+16.4 ms
XTAL = 12.0 MHz
Time-out
–0/+10.9 ms
0 0
1
32.768 ms
16.384 ms
10.923 ms
0 1
4
131.072 ms
65.536 ms
43.691 ms
1 0
16
524.288 ms
262.140 ms
174.76 ms
1 1
64
2.097 sec
1.049 sec
699.05 ms
E =
1.0 MHz
2.0 MHz
3.0 MHz
COPRST — Am/Reset COP Timer Circuitry
$003A
Bit 7
654321
Bit 0
76543210
RESET:
00000000
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For More Information On This Product,
Go to: www.freescale.com
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MC68HC11D0CFBE3R | 功能描述:8位微控制器 -MCU 8B MCU 192RAM 3 MHZ RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| MC68HC11D0CFN2 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:Microcontrollers |
| MC68HC11D0CFN3 | 制造商: 功能描述: 制造商:undefined 功能描述: |
| MC68HC11D0CFNE2 | 功能描述:8位微控制器 -MCU 8B MCU 192 BYTES RAM RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| MC68HC11D0CFNE2R | 功能描述:8位微控制器 -MCU 8B MCU 192 BYTES RAM RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
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