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参数资料
| 型号： | MC68HC11ED0VP2 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, 2 MHz, MICROCONTROLLER, PDIP40 |
| 封装： | PLASTIC, DIP-40 |
| 文件页数： | 33/108页 |
| 文件大小： | 1672K |
| 代理商： | MC68HC11ED0VP2 |
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Technical Summary
MC68HC11ED0 — Rev. 1.0
Central Processor Unit (CPU)
Central Processor Unit (CPU)
3.3.6.4 Negative (N)
The N bit is set if the result of an arithmetic, logic, or data manipulation
operation is negative (MSB = 1). Otherwise, the N bit is cleared. A result
is said to be negative if its most significant bit (MSB) is a 1. A quick way
to test whether the contents of a memory location has the MSB set is to
load it into an accumulator and then check the status of the N bit.
3.3.6.5 I-Interrupt Mask (I)
The interrupt request (IRQ) mask (I bit) is a global mask that disables all
maskable interrupt sources. While the I bit is set, interrupts can become
pending, but the operation of the CPU continues uninterrupted until the
I bit is cleared. After any reset, the I bit is set by default and can be
cleared only by a software instruction. When an interrupt is recognized,
the I bit is set after the registers are stacked, but before the interrupt
vector is fetched. After the interrupt has been serviced, a
return-from-interrupt instruction is normally executed, restoring the
registers to the values that were present before the interrupt occurred.
Normally, the I bit is 0 after a return from interrupt is executed. Although
the I bit can be cleared within an interrupt service routine, "nesting"
interrupts in this way should be done only when there is a clear
understanding of latency and of the arbitration mechanism. Refer to
3.3.6.6 Half Carry (H)
The H bit is set when a carry occurs between bits 3 and 4 of the
arithmetic logic unit during an ADD, ABA, or ADC instruction. Otherwise,
the H bit is cleared. Half carry is used during BCD operations.
3.3.6.7 X-Interrupt Mask (X)
The XIRQ mask (X) bit disables interrupts from the XIRQ pin. After any
reset, X is set by default and must be cleared by a software instruction.
When an XIRQ interrupt is recognized, the X and I bits are set after the
registers are stacked, but before the interrupt vector is fetched. After the
interrupt has been serviced, an RTI instruction is normally executed,
causing the registers to be restored to the values that were present
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For More Information On This Product,
Go to: www.freescale.com
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相关代理商/技术参数 |
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| MC68HC11ED0VP3 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Technical Summary |
| MC68HC11EX | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:APPENDIX A ELECTRICAL CHARACTERISTICS |
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