参数资料
型号: MC68HC11ED0VP2
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 8-BIT, 2 MHz, MICROCONTROLLER, PDIP40
封装: PLASTIC, DIP-40
文件页数: 34/108页
文件大小: 1672K
代理商: MC68HC11ED0VP2
Central Processor Unit (CPU)
Data Types
MC68HC11ED0 — Rev. 1.0
Technical Summary
Central Processor Unit (CPU)
before the interrupt occurred. The X interrupt mask bit is set only by
hardware (RESET or XIRQ acknowledge). X is cleared only by program
instruction (TAP, where the associated bit of A is 0; or RTI, where bit 6
of the value loaded into the CCR from the stack has been cleared).
There is no hardware action for clearing X.
3.3.6.8 STOP Disable (S)
Setting the STOP disable (S) bit prevents the STOP instruction from
putting the M68HC11 into a low-power stop condition. If the STOP
instruction is encountered by the CPU while the S bit is set, it is treated
as a no-operation (NOP) instruction, and processing continues to the
next instruction. S is set by reset; STOP is disabled by default.
3.4 Data Types
The M68HC11 CPU supports four data types:
1. Bit data
2. 8-bit and 16-bit signed and unsigned integers
3. 16-bit unsigned fractions
4. 16-bit addresses
A byte is eight bits wide and can be accessed at any byte location. A
word is composed of two consecutive bytes with the most significant
byte at the lower value address. Because the M68HC11 is an 8-bit CPU,
there are no special requirements for alignment of instructions or
operands.
3.5 Opcodes and Operands
The M68HC11 Family of microcontrollers uses 8-bit opcodes. Each
opcode identifies a particular instruction and associated addressing
mode to the CPU. Several opcodes are required to provide each
instruction with a range of addressing capabilities. Only 256 opcodes
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For More Information On This Product,
Go to: www.freescale.com
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