参数资料
型号: MC68HC11ED0VP2
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 8-BIT, 2 MHz, MICROCONTROLLER, PDIP40
封装: PLASTIC, DIP-40
文件页数: 36/108页
文件大小: 1672K
代理商: MC68HC11ED0VP2
Central Processor Unit (CPU)
Addressing Modes
MC68HC11ED0 — Rev. 1.0
Technical Summary
Central Processor Unit (CPU)
immediate instructions. The effective address is the address of the byte
following the instruction.
3.6.2 Direct
In the direct addressing mode, the low-order byte of the operand
address is contained in a single byte following the opcode, and the
high-order byte of the address is assumed to be $00. Addresses
$00–$FF are thus accessed directly, using 2-byte instructions.
Execution time is reduced by eliminating the additional memory access
required for the high-order address byte. In most applications, this
256-byte area is reserved for frequently referenced data. In M68HC11
MCUs, the memory map can be configured for combinations of internal
registers, RAM, or external memory to occupy these addresses.
3.6.3 Extended
In the extended addressing mode, the effective address of the argument
is contained in two bytes following the opcode byte. These are 3-byte
instructions (or 4-byte instructions if a prebyte is required). One or two
bytes are needed for the opcode and two for the effective address.
3.6.4 Indexed
In the indexed addressing mode, an 8-bit unsigned offset contained in
the instruction is added to the value contained in an index register (IX or
IY). The sum is the effective address. This addressing mode allows
referencing any memory location in the 64-Kbyte address space. These
are 2- to 5-byte instructions, depending on whether a prebyte is required.
3.6.5 Inherent
In the inherent addressing mode, all the information necessary to
execute the instruction is contained in the opcode. Operations that use
only the index registers or accumulators, as well as control instructions
with no arguments, are included in this addressing mode. These are
1- or 2-byte instructions.
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For More Information On This Product,
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