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参数资料
| 型号： | MC68HC11FC0CFU5 |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | Technical Summary 8-Bit Microcontroller |
| 中文描述： | 8-BIT, 6 MHz, MICROCONTROLLER, PQFP64 |
| 封装： | QFP-64 |
| 文件页数： | 39/74页 |
| 文件大小： | 513K |
| 代理商： | MC68HC11FC0CFU5 |
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MOTOROLA
MC68HC11F1/FC0
44
MC68HC11FTS/D
9.2 SCI Registers
TCLR — Clear Baud Rate Counters (TEST)
Bit 6 — Not implemented. Reads always return zero and writes have no effect.
RCKB — SCI Baud-Rate Clock Check (TEST)
SCP[2:0] — SCI Baud Rate Prescaler Selects
SCR[2:0] — SCI Baud Rate Selects
The prescaler bits SCP[2:0] determine the highest baud rate, and the SCR[2:0] bits select an additional
binary submultiple (divide by 1, 2, 4,..., through 128) of this highest baud rate. The result of these two
dividers in series is the 16X receiver baud rate clock. The SCR[2:0] bits are not affected by reset and
can be changed at any time. They should not be changed, however, when an SCI transfer is in progress.
NOTES:
1. A blank table cell indicates that an uncommon rate results.
BAUD — Baud Rate
$x02B
Bit 7
6
5
4
3
2
1
Bit 0
TCLR
SCP2
SCP1
SCP0
RCKB
SCR2
SCR1
SCR0
RESET:
0
U
Table 21 Baud Rate Prescaler Selection
SCP[2:0]
Divide
Internal
Clock By
Prescaler Output1
XTAL =
4.0 MHz
XTAL =
4.9152 MHz
XTAL =
8.0 MHz
XTAL =
10.0 MHz
XTAL =
12.0 MHz
XTAL =
16.0 MHz
XTAL =
20.0 MHz
XTAL =
24.0 MHz
X00
1
62500
76800
125000
156250
187500
250000
312500
375000
001
3
20833
25600
41667
52083
62500
83333
104167
125000
X10
4
15625
19200
31250
38400
46875
62500
76800
93750
X11
13
4800
5908
9600
12019
14423
19200
24038
28846
101
9
—
20830
—
Table 22 Baud Rate Selection
SCR[2:0]
Divide
Prescaler By
Baud Rate
Prescaler
Output =
4800
Prescaler
Output =
9600
Prescaler
Output =
19200
Prescaler
Output =
38400
Prescaler
Output =
76800
0 0 0
1
4800
9600
19200
38400
76800
0 0 1
2
2400
4800
9600
19200
38400
0 1 0
4
1200
2400
4800
9600
19200
0 1 1
8
600
1200
2400
4800
9600
1 0 0
16
300
600
1200
2400
4800
1 0 1
32
150
300
600
1200
2400
1 1 0
64
75
150
300
600
1200
1 1 1
128
—
75
150
300
600
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