参数资料
型号: MC68HC705JB2P
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 8-BIT, OTPROM, 3 MHz, MICROCONTROLLER, PDIP20
封装: PLASTIC, DIP-20
文件页数: 105/128页
文件大小: 2493K
代理商: MC68HC705JB2P
GENERAL RELEASE SPECIFICATION
August 28, 1998
UNIVERSAL SERIAL BUS MODULE
MC68HC705JB2
10-10
REV 1.1
10.2.4.2 USB Reset Signalling
Reset can wake a device from the suspended mode. A device may take up to 10
ms to wake up from the suspended state.
10.2.4.3 Remote Wake-up
The MC68HC705JB2 also supports the remote wake-up feature. The rmware
has the ability to exit suspend mode by signaling a resume state to the upstream
Host or Hub. A non-idle state (“K” state) on the USB data lines is accomplished by
asserting the FRESUM bit in the UCR1 register.
When using the remote wake-up capability, the rmware must wait for at least 5
ms after the bus is in the idle state before sending the remote wake-up resume
signaling. This allows the upstream devices to get into their suspend state and
prepare for propagating resume signaling. The FRESUM bit should be asserted to
cause the resume state on the USB data lines for at least 10ms, but not more than
15ms. Note that the resume signalling is controlled by the FRESUM bit and
meeting the timing specications is dependent on the rmware. When FRESUM is
cleared by rmware, the data lines will return to their high impedance state. Refer
to Section 10.5.5 for more information about how the Force Resume (FRESUM)
bit can be used to initiate the remote wake-up feature.
10.2.5 Low Speed Device
Externally, low speed devices are congured by the position of a pull-up resistor
on the USB D- pin of the MC68HC705JB2. Low speed devices are terminated as
shown in Figure 10-10 with the pull-up on the D- line.
Figure 10-10. External Low Speed Device Conguration
For low speed transmissions, the transmitter’s EOP width must be between
1.25
s and 1.50s. These ranges include timing variations due to differential
buffer delay and rise/fall time mismatches and to noise and other random effects.
A low speed receiver must accept a 670 ns wide SE0 followed by a J transition as
a valid EOP. An SE0 narrower than 330 ns or an SE0 not followed by a J transition
must be rejected as an EOP. An EOP between 330ns and 670ns may be rejected
or accepted as above. Any SE0 that is 2.5
s or wider is automatically a reset.
68HC705JB2
1.5K
D+
D–
3.3V Regulator Out
USB Low Speed Cable
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For More Information On This Product,
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相关PDF资料
PDF描述
MC68HC705JB4P 8-BIT, OTPROM, 3 MHz, MICROCONTROLLER, PDIP28
MC68HC705K1CDW 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PDSO16
MC68HC705K1CP 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PDIP16
MC68HC705K1S 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, CDIP16
MC68HC705K1DW 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PDSO16
相关代理商/技术参数
参数描述
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