参数资料
型号: MC68HC705JB2P
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 8-BIT, OTPROM, 3 MHz, MICROCONTROLLER, PDIP20
封装: PLASTIC, DIP-20
文件页数: 111/128页
文件大小: 2493K
代理商: MC68HC705JB2P
August 28, 1998
GENERAL RELEASE SPECIFICATION
UNIVERSAL SERIAL BUS MODULE
REV 1.1
10-15
10.4.4 USB Control Logic
The USB control logic manages data movement between the CPU and the
transceiver. The control logic handles both transmit and receive operations on the
USB. It contains the logic used to manipulate the transceiver and the endpoint
registers. The logic contains byte count buffers for transmit operations that load
the active transmit endpoints byte count and use this to determine the number of
bytes to transfer. This same buffer is used for receive transactions to count the
number of bytes received and, upon the end of the transaction, transfer that
number to the receive endpoints byte count register.
When transmitting, the control logic handles parallel to serial conversion, CRC
generation, NRZI encoding, and bit stufng.
When Receiving, the control logic handles Sync detection, packet identication,
end of packet detection, bit (un)stufng, NRZI decoding, CRC validation, and
serial to parallel conversion. Errors detected by the control logic include bad CRC,
time-out while waiting for EOP, and bit stufng violations.
10.4.4.1 Data Encoding/Decoding
The USB employs NRZI data encoding when transmitting packets. In NRZI
encoding, a 1 is represented by no change in level and a 0 is represented by a
change in level. Figure 10-16 shows a data stream and the NRZI equivalent and
Figure 10-17 is a ow diagram for NRZI. The high level represents the J state on
the data lines in this and subsequent gures showing NRZI encoding. A string of
zeros causes the NRZI data to toggle each bit time. A string of ones causes long
periods with no transitions in the data.
10.4.4.2 Bit Stufng
In order to ensure adequate signal transitions, bit stufng is employed by the
transmitting device when sending a packet on the USB (see Figure 10-18 and
Figure 10-19). A 0 is inserted after every six consecutive 1’s in the data stream
before the data is NRZI encoded to force a transition in the NRZI data stream.
This gives the receiver logic a data transition at least once every seven bit times to
guarantee the data and clock lock. The receiver must decode the NRZI data,
recognize the stuffed bits, and discard them. Bit stufng is enabled beginning with
the Sync Pattern and throughout the entire transmission. The data “one” that ends
the Sync Pattern is counted as the rst one in a sequence. Bit stufng is always
enforced, without exception. If required by the bit stufng rules, a zero bit will be
inserted even if it is the last bit before the end-of-packet (EOP) signal.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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相关PDF资料
PDF描述
MC68HC705JB4P 8-BIT, OTPROM, 3 MHz, MICROCONTROLLER, PDIP28
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