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| 型号： | MC68HC705T16B |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDIP56 |
| 封装： | PLASTIC, SDIP-56 |
| 文件页数： | 44/128页 |
| 文件大小： | 734K |
| 代理商： | MC68HC705T16B |
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MOTOROLA
2-2
MC68HC05T16
PIN DESCRIPTIONS AND INPUT/OUTPUT PORTS
2
PC0-PC7
40, 39, 37-32
These eight I/O lines comprise port C. The state of any pin is software
programmable. All port C lines are congured as input during power
on or external reset. PC0-3 are push-pull type pins, and PC4-7 are
+12V open-drain pins.
PE0/PWM0 to
PE7/PWM7
54, 55,56, 1
2, 3, 4, 5
These eight I/O lines comprise port E. The state of any pin is software
programmable. All port E lines are congured as input during power
on or external reset.
These pins become PWM outputs by setting the appropriate bits in
the port E Conguration register ($0C). See Section 2.2.2.
PF0-PF7
6-13
These eight I/O lines comprise port F. The state of any pin is software
programmable. All port F lines are congured as input during power
on or external reset.
Other functions are also shared with these pins, and is selected by
setting the appropriate bits in the port F Conguration register ($0D).
See Section 2.2.2.
PWM8, PWM9
6, 7
PWM channels.
These pins are shared with port pins PF0 and PF1, and are selected
by setting port F Conguration register ($0D) bits 0 and 1 respectively.
I, TONE
8. 9
The I pin of the OSD module expands the color selection range by
providing an intensity bit.
The HTONE pin is mainly used for creating transparent background
effect when the background of a character window overlaps the
original TV picture display.
These pins are shared with port pins PF2 and PF3.Selection is by the
port F Conguration register ($0D) bits 2 and 3 respectively.
ADCIN0, ADCIN1
14, 10
These are the two input channels to the analog to digital converter.
ADCIN1 pin is shared with port PF4, and is selected by setting the
port F Conguration register ($0D) bit 4.
SDA, SCL
11, 12
These two pins are the M-Bus interface pins. SDA is the data line, and
SCL is the clock line. These pins are shared with port pins PF5 and
PF6 respectively. Selection is by the port F Conguration register
($0D) bits 5 and 6.
PACIN
13
This is the clock/control input to the pulse accumulator.
This pin is shared with port pin PF7. Selection is by the port F
Conguration register ($0D) bit 7.
R, G, B
50, 49, 48
These are the output pins for OSD R, G, and B videos.
FBKG
47
This is the OSD output pin for blanking out the original TV picture
display so that OSD data can be displayed on the TV screen.
HFBLK, VFBLK
45, 46
These are the OSD input pins for horizontal and vertical yback
signals from the TV set chassis.They are used for synchronizing OSD
signals with TV display.
VCO
43
This OSD pin is the phase detector output pin. With a low-pass lter
this pin controls the frequency of the internal OSD VCO.
RP
42
This is an input pin for biasing the internal OSD VCO.
PIN NAME
56-pin SDIP
PIN No.
DESCRIPTION
TPG
20
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