
Timer Interface Module (TIM1)
Interrupts
MC68HC908GR60A MC68HC908GR48A MC68HC908GR32A
Data Sheet
MOTOROLA
Timer Interface Module (TIM1)
261
or noise. Toggling on output compare can also cause incorrect PWM signal
generation when changing the PWM pulse width to a new, much larger value.
5.
In the TIM1 status control register (T1SC), clear the TIM1 stop bit, TSTOP.
Setting MS0B links channels 0 and 1 and configures them for buffered PWM
operation. The TIM1 channel 0 registers (TCH0H:TCH0L) initially control the
buffered PWM output. TIM1 status control register 0 (TSCR0) controls and
monitors the PWM signal from the linked channels. MS0B takes priority over
MS0A.
Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIM1
overflows. Subsequent output compares try to force the output to a state it is
already in and have no effect. The result is a 0% duty cycle output.
Setting the channel x maximum duty cycle bit (CHxMAX) and setting the TOVx bit
17.4 Interrupts
The following TIM1 sources can generate interrupt requests:
TIM1 overflow flag (TOF) — The TOF bit is set when the TIM1 counter
reaches the modulo value programmed in the TIM1 counter modulo
registers. The TIM1 overflow interrupt enable bit, TOIE, enables TIM1
overflow CPU interrupt requests. TOF and TOIE are in the TIM1 status and
control register.
TIM1 channel flags (CH1F:CH0F) — The CHxF bit is set when an input
capture or output compare occurs on channel x. Channel x TIM CPU
interrupt requests are controlled by the channel x interrupt enable bit,
CHxIE. Channel x TIM CPU interrupt requests are enabled when CHxIE =1.
CHxF and CHxIE are in the TIM1 channel x status and control register.
17.5 Wait Mode
The WAIT instruction puts the MCU in low power-consumption standby mode.
The TIM1 remains active after the execution of a WAIT instruction. In wait mode
the TIM1 registers are not accessible by the CPU. Any enabled CPU interrupt
request from the TIM1 can bring the MCU out of wait mode.
If TIM1 functions are not required during wait mode, reduce power consumption by
stopping the TIM1 before executing the WAIT instruction.