
Timer Interface Module (TIM2)
Interrupts
MC68HC908GR60A MC68HC908GR48A MC68HC908GR32A
Data Sheet
MOTOROLA
Timer Interface Module (TIM2)
283
18.4 Interrupts
The following TIM2 sources can generate interrupt requests:
TIM2 overflow flag (TOF) — The TOF bit is set when the TIM2 counter
reaches the modulo value programmed in the TIM2 counter modulo
registers. The TIM2 overflow interrupt enable bit, TOIE, enables TIM2
overflow interrupt requests. TOF and TOIE are in the TIM2 status and
control register.
TIM2 channel flags (CH5F:CH0F) — The CHxF bit is set when an input
capture or output compare occurs on channel x. Channel x TIM2 CPU
interrupt requests are controlled by the channel x interrupt enable bit,
CHxIE.
18.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low-power standby modes.
18.5.1 Wait Mode
The TIM2 remains active after the execution of a WAIT instruction. In wait mode,
the TIM2 registers are not accessible by the CPU. Any enabled CPU interrupt
request from the TIM2 can bring the MCU out of wait mode.
If TIM2 functions are not required during wait mode, reduce power consumption by
stopping the TIM2 before executing the WAIT instruction.
18.5.2 Stop Mode
The TIM2 is inactive after the execution of a STOP instruction. The STOP
instruction does not affect register conditions or the state of the TIM2 counter. TIM2
operation resumes when the MCU exits stop mode.
18.6 TIM2 During Break Interrupts
A break interrupt stops the TIM2 counter.
The system integration module (SIM) controls whether status bits in other modules
can be cleared during the break state. The BCFE bit in the SIM break flag control
register (SBFCR) enables software to clear status bits during the break state.
(SeeTo allow software to clear status bits during a break interrupt, write a 1 to the BCFE
bit. If a status bit is cleared during the break state, it remains cleared when the MCU
exits the break state.
To protect status bits during the break state, write a 0 to the BCFE bit. With BCFE
at 0 (its default state), software can read and write I/O registers during the break
state without affecting status bits. Some status bits have a 2-step read/write