
Memory
Data Sheet
MC68HC908GR60A MC68HC908GR48A MC68HC908GR32A
62
Memory
MOTOROLA
Use this step-by-step procedure to program a row of FLASH-2 memory:
1.
Set the PGM bit in the FLASH-2 control register (FL2CR). This configures
the memory for program operation and enables the latching of address and
data programming.
2.
Read the FLASH-2 block protect register (FL2BPR).
3.
Write to any FLASH-2 address within the row address range desired with
any data.
4.
Wait for time, tNVS (minimum 10 s).
5.
Set the HVEN bit.
6.
Wait for time, tPGS (minimum 5 s).
7.
Write data byte to the FLASH-2 address to be programmed.
8.
Wait for time, t PROG (minimum 30 s).
9.
Repeat step 7 and 8 until all the bytes within the row are programmed.
10.
Clear the PGM bit.
11.
Wait for time, tNVH (minimum 5 s).
12.
Clear the HVEN bit.
13.
Wait for a time, tRCV, (typically 1 s) after which the memory can be
accessed in normal read mode.
The FLASH programming algorithm flowchart is shown in Figure 2-10.
NOTES:
A. Programming and erasing of FLASH locations can not be performed by code
being executed from the same FLASH array.
B. While these operations must be performed in the order shown, other unrelated
operations may occur between the steps. However, care must be taken to
ensure that these operations do not access any address within the FLASH
array memory space such as the COP control register (COPCTL) at $FFFF.
C. It is highly recommended that interrupts be disabled during program/erase
operations.
D. Do not exceed t PROG maximum or tHV maximum. tHV is defined as the
cumulative high voltage programming time to the same row before next erase.
t
HV must satisfy this condition:
tNVS+ tNVH + tPGS + (tPROG X 64) ≤ tHV maximum
E. The time between each FLASH address change (step 7 to step 7), or the time
between the last FLASH address programmed to clearing the PGM bit (step 7
to step 10) must not exceed the maximum programming time, tPROG maximum.
F. Be cautious when programming the FLASH-2 array to ensure that non-FLASH
locations are not used as the address that is written to when selecting either the
desired row address range in step 3 of the algorithm or the byte to be
programmed in step 7 of the algorithm.