参数资料
型号: MC705P6ACDWER
厂商: Freescale Semiconductor
文件页数: 27/98页
文件大小: 0K
描述: IC MCU 8BIT EPROM 28-SOIC
标准包装: 1,000
系列: HC05
核心处理器: HC05
芯体尺寸: 8-位
速度: 2.1MHz
连通性: SIO
外围设备: POR,WDT
输入/输出数: 21
程序存储器容量: 4.5KB(4.5K x 8)
程序存储器类型: OTP
RAM 容量: 176 x 8
电压 - 电源 (Vcc/Vdd): 3 V ~ 5.5 V
数据转换器: A/D 4x8b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 28-SOIC(0.295",7.50mm 宽)
包装: 带卷 (TR)
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Freescale Semiconductor
33
Chapter 5
Interrupts
5.1 Introduction
The MCU can be interrupted six different ways:
1.
Non-maskable software interrupt instruction (SWI)
2.
External asynchronous interrupt (IRQ)
3.
Input capture interrupt (TIMER)
4.
Output compare interrupt (TIMER)
5.
Timer overflow interrupt (TIMER)
6.
Port A interrupt (if selected via mask option register)
Interrupts cause the processor to save the register contents on the stack and to set the interrupt mask (I
bit) to prevent additional interrupts. Unlike reset, hardware interrupts do not cause the current instruction
execution to be halted, but are considered pending until the current instruction is completed.
When the current instruction is completed, the processor checks all pending hardware interrupts. If
interrupts are not masked (I bit in the condition code register is clear) and the corresponding interrupt
enable bit is set, the processor proceeds with interrupt processing. Otherwise, the next instruction is
fetched and executed. The SWI is executed the same as any other instruction, regardless of the I-bit state.
When an interrupt is to be processed, the CPU puts the register contents on the stack, sets the I bit in the
CCR, and fetches the address of the corresponding interrupt service routine from the vector table at
locations $1FF8 through $1FFF. If more than one interrupt is pending when the interrupt vector is fetched,
the interrupt with the highest vector location shown in Table 5-1 will be serviced first.
An RTI instruction is used to signify when the interrupt software service routine is completed. The RTI
instruction causes the CPU state to be recovered from the stack and normal processing to resume at the
next instruction that was to be executed when the interrupt took place. Figure 5-1 shows the sequence of
events that occurs during interrupt processing.
Table 5-1. Vector Addresses for Interrupts and Reset
Register
Flag
Name
Interrupts
CPU
Interrupt
Vector
Address
N/A
Reset
RESET
$1FFE–$1FFF
N/A
Software
SWI
$1FFC–$1FFD
N/A
External Interrupt
IRQ
$1FFA–$1FFB
TSR
ICF
Timer Input Capture
TIMER
$1FF8–$1FF9
TSR
OCF
Timer Output Compare
TIMER
$1FF8–$1FF9
TSR
TOF
Timer Overflow
TIMER
$1FF8–$1FF9
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