参数资料
型号: MC705P6ACDWER
厂商: Freescale Semiconductor
文件页数: 33/98页
文件大小: 0K
描述: IC MCU 8BIT EPROM 28-SOIC
标准包装: 1,000
系列: HC05
核心处理器: HC05
芯体尺寸: 8-位
速度: 2.1MHz
连通性: SIO
外围设备: POR,WDT
输入/输出数: 21
程序存储器容量: 4.5KB(4.5K x 8)
程序存储器类型: OTP
RAM 容量: 176 x 8
电压 - 电源 (Vcc/Vdd): 3 V ~ 5.5 V
数据转换器: A/D 4x8b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 28-SOIC(0.295",7.50mm 宽)
包装: 带卷 (TR)
Port D
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Freescale Semiconductor
39
Figure 6-3. Port C I/O Circuitry
6.5 Port D
Port D is a 2-bit port with one bidirectional pin (PD5) and one input-only pin (PD7). Pin PD7 is shared with
the 16-bit timer. The port D data register is located at address $0003 and its data direction register (DDR)
is located at address $0007. The contents of the port D data register are indeterminate at initial powerup
and must be initialized by user software. Reset does not affect the data registers, but clears the DDRs,
thereby setting PD5 to input mode. Writing a 1 to DDR bit 5 sets PD5 to output mode (see Figure 6-4).
Port D may be used for general I/O applications regardless of the state of the 16-bit timer. Since PD7 is
an input-only line, its state can be read from the port D data register at any time.
Figure 6-4. Port D I/O Circuitry
6.6 I/O Port Programming
Each pin on port A through port D (except pin 7 of port D) can be programmed as an input or an output
under software control as shown in Table 6-1, Table 6-2, Table 6-3, and Table 6-4. The direction of a pin
is determined by the state of its corresponding bit in the associated port data direction register (DDR). A
pin is configured as an output if its corresponding DDR bit is set to a logic 1. A pin is configured as an
input if its corresponding DDR bit is cleared to a logic 0.
READ $0002
WRITE $0002
READ $0006
DATA
REGISTER BIT
I/O
PIN
OUTPUT
INTERNAL HC05
DATA BUS
RESET
(RST)
WRITE $0006
DATA DIRECTION
REGISTER BIT
READ $0003
WRITE $0003
READ $0007
DATA
REGISTER BIT
I/O
PIN
OUTPUT
INTERNAL HC05
DATA BUS
RESET
(RST)
WRITE $0007
DATA DIRECTION
REGISTER BIT
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