参数资料
型号: MC705P6ACDWER
厂商: Freescale Semiconductor
文件页数: 42/98页
文件大小: 0K
描述: IC MCU 8BIT EPROM 28-SOIC
标准包装: 1,000
系列: HC05
核心处理器: HC05
芯体尺寸: 8-位
速度: 2.1MHz
连通性: SIO
外围设备: POR,WDT
输入/输出数: 21
程序存储器容量: 4.5KB(4.5K x 8)
程序存储器类型: OTP
RAM 容量: 176 x 8
电压 - 电源 (Vcc/Vdd): 3 V ~ 5.5 V
数据转换器: A/D 4x8b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 28-SOIC(0.295",7.50mm 宽)
包装: 带卷 (TR)
Timer I/O Registers
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Freescale Semiconductor
47
8.3.1 Timer Control Register
The timer control register (TCR), shown in Figure 8-2, performs these functions:
Enables input capture interrupts
Enables output compare interrupts
Enables timer overflow interrupts
Controls the active edge polarity of the TCAP signal
Controls the active level of the TCMP output
ICIE — Input Capture Interrupt Enable
This read/write bit enables interrupts caused by an active signal on the TCAP pin. Resets clear the
ICIE bit.
1 = Input capture interrupts enabled
0 = Input capture interrupts disabled
OCIE — Output Compare Interrupt Enable
This read/write bit enables interrupts caused by an active signal on the TCMP pin. Resets clear the
OCIE bit.
1 = Output compare interrupts enabled
0 = Output compare interrupts disabled
TOIE — Timer Overflow Interrupt Enable
This read/write bit enables interrupts caused by a timer overflow. Reset clear the TOIE bit.
1 = Timer overflow interrupts enabled
0 = Timer overflow interrupts disabled
IEDG — Input Edge
The state of this read/write bit determines whether a positive or negative transition on the TCAP pin
triggers a transfer of the contents of the timer register to the input capture register. Resets have no
effect on the IEDG bit.
1 = Positive edge (low to high transition) triggers input capture
0 = Negative edge (high to low transition) triggers input capture
OLVL — Output Level
The state of this read/write bit determines whether a logic 1 or logic 0 appears on the TCMP pin when
a successful output compare occurs. Resets clear the OLVL bit.
1 = TCMP goes high on output compare
0 = TCMP goes low on output compare
Address:
$0012
Bit 7
654321
Bit 0
Read:
ICIE
OCIE
TOIE
000
IEDG
OLVL
Write:
Reset:
000000
U
0
= Unimplemented
U = Undetermined
Figure 8-2. Timer Control Register (TCR)
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