参数资料
型号: MC8640DTHX1250HE
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 1250 MHz, MICROPROCESSOR, CBGA1023
封装: 33 X 33 MM, CERAMIC, FCBGA-1023
文件页数: 120/130页
文件大小: 1495K
代理商: MC8640DTHX1250HE
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
9
Electrical Characteristics
Figure 2 shows the undershoot and overshoot voltages at the interfaces of the MPC8640.
Figure 2. Overshoot/Undershoot Voltage for D
n
_M/O/L/TVIN
The MPC8640 core voltage must always be provided at nominal VDD_Coren (See Table 2 for actual
recommended core voltage). Voltage to the processor interface I/Os are provided through separate sets of
supply pins and must be provided at the voltages shown in Table 2. The input voltage threshold scales with
respect to the associated I/O supply voltage. OVDD and L/TVDD based receivers are simple CMOS I/O
circuits and satisfy appropriate LVCMOS type specifications. The DDR SDRAM interface uses a
single-ended differential receiver referenced to each externally supplied Dn_MVREF signal (nominally set
to Dn_GVDD/2) as is appropriate for the (SSTL-18 and SSTL-25) electrical signaling standards.
GND
GND – 0.3 V
GND – 0.7 V
Not to Exceed 10%
L/T/D
n_G/O/X/SVDD + 20%
L/T/D
n_G/O/X/SVDD
L/T/D
n_G/O/X/SVDD + 5%
of tCLK
1
1. tCLK references clocks for various functional blocks as follows:
VIH
VIL
Note:
DDRn = 10% of Dn_MCK period
eTSECn = 10% of ECn_GTX_CLK125 period
Local Bus = 10% of LCLK[0:2] period
I2C = 10% of SYSCLK
JTAG = 10% of SYSCLK
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