参数资料
型号: MC8640DTHX1250HE
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 1250 MHz, MICROPROCESSOR, CBGA1023
封装: 33 X 33 MM, CERAMIC, FCBGA-1023
文件页数: 39/130页
文件大小: 1495K
代理商: MC8640DTHX1250HE
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3
16
Freescale Semiconductor
Input Clocks
4.1.1
SYSCLK and Spread Spectrum Sources
Spread spectrum clock sources are an increasingly popular way to control electromagnetic interference
emissions (EMI) by spreading the emitted noise to a wider spectrum and reducing the peak noise
magnitude in order to meet industry and government requirements. These clock sources intentionally add
long-term jitter to diffuse the EMI spectral content. The jitter specification given in Table 8 considers
short-term (cycle-to-cycle) jitter only and the clock generator’s cycle-to-cycle output jitter should meet the
MPC8640 input cycle-to-cycle jitter requirement. Frequency modulation and spread are separate concerns,
and the MPC8640 is compatible with spread spectrum sources if the recommendations listed in Table 9 are
observed.
It is imperative to note that the processor’s minimum and maximum SYSCLK, core, and VCO frequencies
must not be exceeded regardless of the type of clock source. Therefore, systems in which the processor is
operated at its maximum rated e600 core frequency should avoid violating the stated limits by using
down-spreading only.
SDn_REF_CLK and SDn_REF_CLK were designed to work with a spread spectrum clock (+0 to 0.5%
spreading at 30-33 kHz rate is allowed), assuming both ends have same reference clock. For better results,
use a source without significant unintended modulation.
SYSCLK duty cycle
tKHK/tSYSCLK
40
60
%
3
SYSCLK jitter
150
ps
4, 5
Notes:
1. Caution: The MPX clock to SYSCLK ratio and e600 core to MPX clock ratio settings must be chosen such that the resulting
SYSCLK frequency, e600 (core) frequency, and MPX clock frequency do not exceed their respective maximum or minimum
Ratio,for ratio settings.
2. Rise and fall times for SYSCLK are measured at 0.4 V and 2.7 V.
3. Timing is guaranteed by design and characterization.
4. This represents the short term jitter only and is guaranteed by design.
5. The SYSCLK driver’s closed loop jitter bandwidth should be <500 kHz at –20 dB. The bandwidth must be set low to allow
cascade-connected PLL-based devices to track SYSCLK drivers with the specified jitter. Note that the frequency modulation
for SYSCLK reduces significantly for the spread spectrum source case. This is to guarantee what is supported based on
design.
Table 9. Spread Spectrum Clock Source Recommendations
At recommended operating conditions. See Table 2.
Parameter
Min
Max
Unit
Notes
Frequency modulation
50
kHz
1
Frequency spread
1.0
%
1, 2
Notes:
1. Guaranteed by design.
2. SYSCLK frequencies resulting from frequency spreading, and the resulting core and VCO frequencies, must meet the
minimum and maximum specifications given in Table 8.
Table 8. SYSCLK AC Timing Specifications (continued)
At recommended operating conditions (see Table 2) with OVDD = 3.3 V ± 165 mV.
Parameter
Symbol
Min
Typical
Max
Unit
Notes
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