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| 型号： | MC88916DW70 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 88916 SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PDSO20 |
| 封装： | PLASTIC, SOIC-20 |
| 文件页数： | 1/10页 |
| 文件大小： | 503K |
| 代理商： | MC88916DW70 |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Motorola, Inc. 1995
1
11/93
REV 2
Low Skew CMOS PLL Clock
Driver With Processor Reset
The MC88916 Clock Driver utilizes phase–locked loop technology to
lock its low skew outputs’ frequency and phase onto an input reference
clock. It is designed to provide clock distribution for CISC microprocessor
or single processor RISC systems. The RST_IN/RST_OUT(LOCK) pins
provide a processor reset function designed specifically for the
MC68/EC/LC030/040 microprocessor family. The 88916 comes in two
speed grades: 70 and 80MHz. These frequencies correspond to the
2X_Q maximum output frequency. The two grades should be ordered as
the MC88916DW70 and MC88916DW80, respectively.
Provides Performance Required to Drive 68030 Microprocessor Family
as well as the 33 and 40MHz 68040 Microprocessors
Three Outputs (Q0–Q2) With Output–Output Skew <500ps and Six
Outputs Total (Q0–Q2, Q3, 2X_Q,) With <1ns Skew Each Being Phase
and Frequency Locked to the SYNC Input
The Phase Variation From Part–to–Part Between SYNC and the ‘Q’
Outputs Is Less Than 600ps (Derived From the TPD Specification,
Which Defines the Part–to–Part Skew)
SYNC Input Frequency Range From 5MHZ to 2X_Q FMax/4
Additional Outputs Available at 2X and ÷2 the System ‘Q’ Frequency.
Also a Q (180
° Phase Shift) Output Available.
All Outputs Have ±36mA Drive (Equal High and Low) CMOS Levels.
Can Drive Either CMOS or TTL Inputs. All Inputs Are TTL–Level
Compatible
Test Mode Pin (PLL_EN) Provided for Low Frequency Testing
The PLL allows the high current, low skew outputs to lock onto a single clock input and distribute it with essentially zero delay
to multiple locations on a board. The PLL also allows the MC88916 to multiply a low frequency input clock and distribute it locally
at a higher (2X) system frequency.
Three ‘Q’ outputs (Q0–Q2) are provided with less than 500ps skew between their rising edges. The Q3 output is inverted (180
°
phase shift) from the ‘Q’ outputs. A 2X_Q output runs at twice the ‘Q’ output frequency. The 2X_Q output does not meet the
stringent duty cycle requirement of the 20 and 25Mhz 68040 microprocessor PCLK input. The 88920 has been designed
specifically to provide the 68040 PCLK and BCLK inputs for the low frequency 68040 microprocessor. 68040 designers should
refer to the 88920 data sheet for more details. For the 33 and 40MHz 68040, the 2X_Q output will meet the duty cycle
requirements of the PCLK input. The Q/2 output runs at 1/2 the ‘Q’ frequency. This output is fed back internally, providing a fixed
2X multiplication from the ‘Q’ outputs to the SYNC input. Since the feedback is done internally (no external feedback pin is
provided) the input/output frequency relationships are fixed.
In normal phase–locked operation the PLL_EN pin is held high. Pulling the PLL_EN pin low disables the VCO and puts the
88916 in a static ‘test mode’. In this mode there is no frequency limitation on the input clock, which is necessary for a low
frequency board test environment.
The RST_OUT(LOCK) pin doubles as a phase–lock indicator. When the RST_IN pin is held high, the open drain RST_OUT
pin will be pulled actively low until phase–lock is achieved. When phase–lock occurs, the RST_OUT(LOCK) is released and a
pull–up resistor will pull the signal high. To give a processor reset signal, the RST_IN pin is toggled low, and the
RST_OUT(LOCK) pin will stay low for 1024 cycles of the ‘Q’ output frequency after the RST_IN pin is brought back high.
Description of the RST_IN/RST_OUT(LOCK) Functionality
The RST_IN and RST_OUT(LOCK) pins provide a 68030/040 processor reset function, with the RST_OUT pin also acting as
a lock indicator. If the RST_IN pin is held high during system power–up, the RST_OUT pin will be in the low state until steady
state phase/frequency lock to the input reference is achieved. 1024 ‘Q’ output cycles after phase–lock is achieved the
RST_OUT(LOCK) pin will go into a high impedance state, allowing it to be pulled high by an external pull–up resistor (see the
AC/DC specs for the characteristics of the RST_OUT(LOCK) pin). If the RST_IN pin is held low during power–up, the
RST_OUT(LOCK) pin will remain low.
MC88916
LOW SKEW CMOS PLL
CLOCK DRIVER WITH
PROCESSOR RESET
DW SUFFIX
SOIC PACKAGE
CASE 751D–04
20
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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DATA SHEET
MC88916
IDT Low Skew CMOS PLL Clock Drivers With Processor Reset
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MC88916
1
Low Skew CMOS PLL Clock Drivers
With Processor Reset
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| MC88916DW80 | 功能描述:IC DRIVER CLK PLL 80MHZ 20-SOIC RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是 主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT |
| MC88916DWR2 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:LOW SKEW CMOS PLL CLOCK DRIVER WITH PROCESSOR RESET |
| MC88916EG70 | 功能描述:IC PLL CLOCK DRIVER 20-SOIC RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是 主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT |
| MC88916EG70R2 | 功能描述:IC PLL CLOCK DRIVER 20-SOIC RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是 主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT |
| MC88916EG80 | 功能描述:时钟驱动器及分配 FSL 5V CMOS PLL Clk Driver w/ Reset RoHS:否 制造商:Micrel 乘法/除法因子:1:4 输出类型:Differential 最大输出频率:4.2 GHz 电源电压-最大: 电源电压-最小:5 V 最大工作温度:+ 85 C 封装 / 箱体:SOIC-8 封装:Reel |
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