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参数资料
| 型号： | MC88916DW70 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 88916 SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PDSO20 |
| 封装： | PLASTIC, SOIC-20 |
| 文件页数： | 7/10页 |
| 文件大小： | 503K |
| 代理商： | MC88916DW70 |
MC88916
MOTOROLA
TIMING SOLUTIONS
BR1333 — REV 5
6
Application Notes
1. Several specifications can only be measured when the
MC88916 is in phase–locked operation. It is not possible
to have the part in phase–lock on ATE (automated test
equipment). Statistical characterization techniques were
used to guarantee those specifications which cannot be
measured on the ATE. MC88916 units were fabricated
with key transistor properties intentionally varied to create
a 14 cell designed experimental matrix. IC performance
was characterized over a range of transistor properties
(represented by the 14 cells) in excess of the expected
process variation of the wafer fabrication area. IC
performance to each specification and fab variation were
used to set performance limits of ATE testable
specifications within those which are to be guaranteed by
statistical characterization. In this way, all units passing
the ATE test will meet or exceed the non–tested
specifications limits.
2. A 1M
resistor tied to either Analog VCC or Analog GND,
as shown in Figure 2, is required to ensure no jitter is
present on the MC88916 outputs. This technique causes
a phase offset between the SYNC input and the Q0
output, measured at the pins. The tPD spec describes how
this offset varies with process, temperature, and voltage.
The specs were arrived at by measuring the phase
relationship for the 14 lots described in note 1 while the
part was in phase–locked operation. The actual
measurements were made with a 10MHz SYNC input
(1.0ns edge rate from 0.8V to 2.0V). The phase
measurements were made at 1.5V. See Figure 2 for a
graphical description.
3. The pulse width spec for the Q and 2Q_X outputs is
referenced to a VCC/2 threshold. To translate this down to
a 1.5V reference with the same pulse width tolerance, the
termination scheme pictured in Figure 3 must be used.
This termination scheme is required to drive the PCLK
input of the 68040 microprocessor with the 88916 outputs.
4. The tPD spec (SYNC to Q/2) guarantees how close the
Q/2 output will be locked to the reference input connected
to the SYNC input (including temperature and voltage
variation). This also tells what the skew from the Q/2
output on one part connected to a given reference input, to
the Q/2 output on one or more parts connected to that
reference input (assuming equal delay from the reference
input to the SYNC input of each part). Therefore the tPD
spec is equivalent to a part–to–part specification.
However, to correctly predict the skew from a given output
on one part to any other output on one or more other parts,
the distribution of each output in relation to the SYNC
input must be known. This distribution for the MC88916 is
provided in Table 1.
TABLE 1.
Distribution of Each Output versus SYNC
Output
–(ps)
+(ps)
2X_Q
Q0
Q1
Q2
Q3
Q/2
TBD
Figure 2. Depiction of the Fixed SYNC to Q0 Offset (tPD) Which Is Present
When a 1M
Resistor Is Tied to VCC or Ground
1M
REFERENCE
RESISTOR
EXTERNAL
LOOP FILTER
330
0.1
F
ANALOG GND
RC1
R2
C1
WITH THE 1M
RESISTOR TIED IN THIS FASHION THE TPD
SPECIFICATION, MEASURED AT THE INPUT PINS IS:
SYNC INPUT
Q0 OUTPUT
2.25ns
OFFSET
3V
5V
tPD = 2.25ns ± 1.0ns (TYPICAL VALUES)
SYNC INPUT
Q0 OUTPUT
–0.8ns
OFFSET
3V
5V
1M
REFERENCE
RESISTOR
330
0.1
F
ANALOG GND
ANALOG VCC
R2
C1
WITH THE 1M
RESISTOR TIED IN THIS FASHION THE TPD
SPECIFICATION, MEASURED AT THE INPUT PINS IS:
tPD = –0.80ns ± 0.30ns
RC1
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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MC88916
Low Skew CMOS PLL Clock Drivers With Processor Reset
NETCOM
IDT Low Skew CMOS PLL Clock Drivers With Processor Reset
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MC88916
6
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