参数资料
型号: MC88916DW70
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 时钟及定时
英文描述: 88916 SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PDSO20
封装: PLASTIC, SOIC-20
文件页数: 5/10页
文件大小: 503K
代理商: MC88916DW70
MC88916
MOTOROLA
TIMING SOLUTIONS
BR1333 — REV 5
4
Figure 1. MC88916 Logic Block Diagram
Q
R
D
Q1
Q
R
D
Q2
Q
R
D
Q3
Q
R
D
Q/2
Q
R
D
Q0
VCO
CH
PUMP
PFD
SYNC
PLL_EN
MR
POWER–ON
RESET
01
LOCK INDICATOR AND
RESET_OUT 1024 CYCLE
COUNT CIRCUITRY
RST_IN
2X_Q
RST_OUT
SYNC INPUT TIMING REQUIREMENTS
Symbol
Parameter
Minimum
Maximum
Unit
tRISE/FALL
SYNC Input
Rise/Fall Time, SYNC Input
From 0.8V to 2.0V
5.0
ns
tCYCLE,
Input Clock Period
‘DW70
‘DW80
SYNC Input
57
50
200
ns
Duty Cycle
Duty Cycle, SYNC Input
50%
± 25%
FREQUENCY SPECIFICATIONS (TA = –40°C to +85°C; VCC = 5.0V ± 5%)
Guaranteed Minimum
Symbol
Parameter
MC88916DW70
MC88916DW80
Unit
Fmax (2X_Q)
Maximum Operating Frequency, 2X_Q Output
70
80
MHz
Fmax (‘Q’)
Maximum Operating Frequency, Q0–Q2, Q3 Outputs
35
40
MHz
1. Maximum Operating Frequency is guaranteed with the 88916 in a phase–locked condition, and all outputs loaded at 50
terminated to VCC/2.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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MC88916
Low Skew CMOS PLL Clock Drivers With Processor Reset
NETCOM
IDT Low Skew CMOS PLL Clock Drivers With Processor Reset
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MC88916
4
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