- 您现在的位置：买卖IC网 > PDF目录26811 > MC88LV926DW (INTEGRATED DEVICE TECHNOLOGY INC) 88LV SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PDSO20 PDF资料下载
参数资料
| 型号： | MC88LV926DW |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 88LV SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PDSO20 |
| 封装： | PLASTIC, SOIC-20 |
| 文件页数： | 10/11页 |
| 文件大小： | 285K |
| 代理商： | MC88LV926DW |
Advanced Clock Drivers Device Data
8
Freescale Semiconductor
MC88LV926
NOTES CONCERNING LOOP FILTER AND
BOARD LAYOUT ISSUES
1.
Figure 7 shows a loop filter and analog isolation
scheme which will be effective in most applications. The
following guidelines should be followed to ensure stable
and jitter-free operation:
1a. All loop filter and analog isolation components should
be tied as close to the package as possible. Stray
current passing through the parasitics of long traces can
cause undesirable voltage transients at the RC1 pin.
1b. The 47
Ω resistors, the 10 μF low frequency bypass
capacitor, and the 0.1
μF high frequency bypass
capacitor form a wide bandwidth filter that will make the
88LV926 PLL insensitive to voltage transients from the
system digital VCC supply and ground planes. This filter
will typically ensure that a 100mV step deviation on the
digital VCC supply will cause no more than a 100 ps
phase deviation on the 88LV926 outputs. A 250 mV
step deviation on VCC using the recommended filter
values will cause no more than a 250 ps phase
deviation; if a 25
μF bypass capacitor is used (instead of
10
μF) a 250 mV V
CC step will cause no more than a
100 ps phase deviation.
If good bypass techniques are used on a board design
near components which may cause digital VCC and
ground noise, the above described VCC step deviations
should not occur at the 88LV926's digital VCC supply.
The purpose of the bypass filtering scheme shown in
Figure 6 is to give the 88LV926 additional protection
from the power supply and ground plane transients that
can occur in a high frequency, high speed digital system.
1c. There are no special requirements set forth for the loop
filter resistors (470 K and 33 0
Ω). The loop filter
capacitor (0.1uF) can be a ceramic chip capacitor, the
same as a standard bypass capacitor.
1d. The 470 K reference resistor injects current into the
internal charge pump of the PLL, causing a fixed offset
between the outputs and the SYNC input. This also
prevents excessive jitter caused by inherent PLL dead–
band. If the VCO (2X_Q output) is running above
40 MHz, the 470 K resistor provides the correct amount
of current injection into the charge pump (2–3
μA). If the
VCO is running below 40 MHz, a 1 M
Ω reference
resistor should be used (instead of 470 K).
2.
In addition to the bypass capacitors used in the analog
filter of Figure 7, there should be a 0.1
μF bypass
capacitor between each of the other (digital) four VCC
pins and the board ground plane. This will reduce output
switching noise caused by the 88LV926 outputs, in
addition to reducing potential for noise in the ‘analog'
section of the chip. These bypass capacitors should
also be tied as close to the 88LV926 package as
possible.
Figure 7. Recommended Loop Filter and Analog Isolation Scheme for the MC88LV926
47
Ω
Board VCC
0.1
μF (Loop Filter
Cap)
330
Ω
470 K
Ω or
1 M
Ω
0.1
μF High
Freq Bias
10
μF Low
Freq Bias
47
Ω
Board GND
6
Analog Loop Filter/VCO Section
of the MC88LV926 20-Pin SOIC
Package (not drawn to scale)
A separate Analog power suppy is not necessary and should not be used.
Following these prescribed guidelines is all that is necessary to use the
MC88LV926 in a normal digital environment.
NOTE: Further loop optimization may occur.
RC1
7
Analog VCC
5
Analog GND
MC88LV926
Low Skew CMOS PLL 68060 Clock Driver
NETCOM
IDT Low Skew CMOS PLL 68060 Clock Driver
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MC88LV926
8
相关PDF资料 |
PDF描述 |
|---|---|
| MD2FLDL-TTL-35G | ACTIVE DELAY LINE, TRUE OUTPUT, DSO6 |
| MD2FLDL-TTL-7F | ACTIVE DELAY LINE, TRUE OUTPUT, DIP6 |
| MD2FLDL-TTL-80G | ACTIVE DELAY LINE, TRUE OUTPUT, DSO6 |
| MD2FLDL-TTL-200G | ACTIVE DELAY LINE, TRUE OUTPUT, DSO6 |
| MD2FLDL-TTL-150T | ACTIVE DELAY LINE, TRUE OUTPUT, DSO6 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MC88LV926DWR2 | 功能描述:IC DRIVER CLK PLL 66MHZ 20-SOIC RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是 主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT |
| MC88LV926EG | 功能描述:IC PLL CLOCK DRIVER 20-SOIC RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是 主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT |
| MC88LV926EGR2 | 功能描述:IC PLL CLOCK DRIVER 20-SOIC RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是 主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT |
| MC88PL117 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:CMOS PLL CLOCK DRIVER |
| MC88PL117FN | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:CMOS PLL CLOCK DRIVER |
发布紧急采购，3分钟左右您将得到回复。