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| 型号： | MC88LV926DW |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 88LV SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PDSO20 |
| 封装： | PLASTIC, SOIC-20 |
| 文件页数： | 8/11页 |
| 文件大小： | 285K |
| 代理商： | MC88LV926DW |
Advanced Clock Drivers Device Data
6
Freescale Semiconductor
MC88LV926
APPLICATION NOTES
1.
Statistical characterization techniques were used to
guarantee those specifications which cannot be
measured on the ATE. MC88LV926 units were
fabricated with key transistor properties intentionally
varied to create a 14 cell designed experimental matrix.
IC performance was characterized over a range of
transistor properties (represented by the 14 cells) in
excess of the expected process variation of the wafer
fabrication area. IC performance to each specification
and fab variation were used to set performance limits of
ATE testable specifications within those which are to be
guaranteed by statistical characterization. In this way, all
units passing the ATE test will meet or exceed the non-
tested specifications limits.
2.
A 470 K
Ω or 1 MΩ resistor tied to either Analog V
CC or
Analog GND, as shown in Figure 3, is required to
ensure no jitter is present on the MC88LV926 outputs.
This technique causes a phase offset between the
SYNC input and the Q0 output, measured at the pins.
The tPD spec describes how this offset varies with
process, temperature, and voltage. The specs were
arrived at by measuring the phase relationship for the
14 lots described in note 1 while the part was in phase-
locked operation. The actual measurements were made
with a 10 MHz SYNC input (1.0 ns edge rate from 0.8 V
to 2.0 V). The phase measurements were made at
1.5 V. See Figure 3 for a graphical description.
3.
Two specs (tRISE/FALL and tPULSE Width 2X_Q output,
see AC Specifications) guarantee that the MC88LV926
meets the 33 MHz and 66 MHz 68060 P-Clock input
specification.
Figure 3. Depiction of the Fixed SYNC to Q0 Offset (tPD) Which Is Present
When a 470 K
Ω Resistor Is Tied to V
CC or Ground
Figure 4. RST_OUT Test Circuit
1 M
Ω or 470 K Ω
Reference
Resistor
External
Loop Filter
330
Ω
0.1
μF
Analog GND
RC1
R2
C1
With the 470 K
Ω resistor tied in this fashion, the TPD specification
measured at the input pins is:
SYNC InputT
Q0 OutputT
2.25 ns
Offset
3 V
5 V
tPD = 2.25 ns ± 1.0 ns (Typical Values)
SYNC Input
Q0 Output
–0.8 ns
Offset
3 V
5 V
1 M
Ω or 470 KΩ
Reference
Resistor
330
Ω
0.1
μF
Analog GND
Analog VCC
R2
C1
With the 470 K
Ω resistor tied in this fashion, the TPD specification
measured at the input pin is:
tPD = –0.80 ns ± 0.30 ns
RC1
Analog GND
CL
VCC
1 K
RST_OUT Pin
Internal
Logic
MC88LV926
Low Skew CMOS PLL 68060 Clock Driver
NETCOM
IDT Low Skew CMOS PLL 68060 Clock Driver
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MC88LV926
6
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