Central Processor Unit (CPU)
CPU Registers
MC68HC908QF4 — Rev. 1.0
Data Sheet
MOTOROLA
Central Processor Unit (CPU)
61
7.3.2 Index Register
The 16-bit index register allows indexed addressing of a 64-Kbyte memory space.
H is the upper byte of the index register, and X is the lower byte. H:X is the
concatenated 16-bit index register.
In the indexed addressing modes, the CPU uses the contents of the index register
to determine the conditional address of the operand.
The index register can serve also as a temporary data storage location.
7.3.3 Stack Pointer
The stack pointer is a 16-bit register that contains the address of the next location
on the stack. During a reset, the stack pointer is preset to $00FF. The reset stack
pointer (RSP) instruction sets the least significant byte to $FF and does not affect
the most significant byte. The stack pointer decrements as data is pushed onto the
stack and increments as data is pulled from the stack.
In the stack pointer 8-bit offset and 16-bit offset addressing modes, the stack
pointer can function as an index register to access data on the stack. The CPU
uses the contents of the stack pointer to determine the conditional address of the
operand.
NOTE:
The location of the stack is arbitrary and may be relocated anywhere in
random-access memory (RAM). Moving the SP out of page 0 ($0000 to $00FF)
frees direct address (page 0) space. For correct operation, the stack pointer must
point only to RAM locations.
Bit
15
14
13
12
11
10
987654321
Bit
0
Read:
Write:
Reset:
00000000
XXXXXXXX
X = Indeterminate
Figure 7-3. Index Register (H:X)
Bit
15
14
13
12
11
10
987654321
Bit
0
Read:
Write:
Reset:
0000000011111111
Figure 7-4. Stack Pointer (SP)
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Freescale Semiconductor, Inc.
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