System Integration Module (SIM)
Data Sheet
MC68HC908QF4 — Rev. 1.0
122
System Integration Module (SIM)
MOTOROLA
14.3.1 Bus Timing
In user mode, the internal bus frequency is the oscillator frequency (BUSCLKX4)
divided by four.
14.3.2 Clock Start-Up from POR
When the power-on reset module generates a reset, the clocks to the CPU and
peripherals are inactive and held in an inactive phase until after the 4096
BUSCLKX4 cycle POR time out has completed. The IBUS clocks start upon
completion of the time out.
14.3.3 Clocks in Stop Mode and Wait Mode
Upon exit from stop mode by an interrupt or reset, the SIM allows BUSCLKX4 to
clock the SIM counter. The CPU and peripheral clocks do not become active until
after the stop delay time out. This time out is selectable as 4096 or 32 BUSCLKX4
In wait mode, the CPU clocks are inactive. The SIM also produces two sets of
clocks for other modules. Refer to the wait mode subsection of each module to see
if the module is active or inactive in wait mode. Some modules can be programmed
to be active in wait mode.
14.4 Reset and System Initialization
The MCU has these reset sources:
Power-on reset module (POR)
External reset pin (RST)
Computer operating properly module (COP)
Low-voltage inhibit module (LVI)
Illegal opcode
Illegal address
All of these resets produce the vector $FFFE–FFFF ($FEFE–FEFF in monitor
mode) and assert the internal reset signal (IRST). IRST causes all registers to be
returned to their default values and all modules to be returned to their reset states.
An internal reset clears the SIM counter (see 14.5 SIM Counter), but an external
reset does not. Each of the resets sets a corresponding bit in the SIM reset status
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Freescale Semiconductor, Inc.
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