External Interrupt (IRQ)
IRQ Status and Control Register
MC68HC908QF4 — Rev. 1.0
Data Sheet
MOTOROLA
External Interrupt (IRQ)
77
To allow software to clear the IRQ latch during a break interrupt, write a 1 to the
BCFE bit. If a latch is cleared during the break state, it remains cleared when the
MCU exits the break state.
To protect the latches during the break state, write a 0 to the BCFE bit. With BCFE
at 0 (its default state), writing to the ACK bit in the IRQ status and control register
during the break state has no effect on the IRQ latch.
8.6 IRQ Status and Control Register
The IRQ status and control register (ISCR) controls and monitors operation of the
The ISCR has the following functions:
Shows the state of the IRQ flag
Clears the IRQ latch
Masks IRQ and interrupt request
Controls triggering sensitivity of the IRQ interrupt pin
IRQF — IRQ Flag
This read-only status bit is high when the IRQ interrupt is pending.
1 = IRQ interrupt pending
0 = IRQ interrupt not pending
ACK — IRQ Interrupt Request Acknowledge Bit
Writing a 1 to this write-only bit clears the IRQ latch. ACK always reads as 0.
Reset clears ACK.
IMASK — IRQ Interrupt Mask Bit
Writing a 1 to this read/write bit disables IRQ interrupt requests. Reset clears
IMASK.
1 = IRQ interrupt requests disabled
0 = IRQ interrupt requests enabled
MODE — IRQ Edge/Level Select Bit
This read/write bit controls the triggering sensitivity of the IRQ pin. Reset clears
MODE.
1 = IRQ interrupt requests on falling edges and low levels
0 = IRQ interrupt requests on falling edges only
Address: $001D
Bit 7
654321
Bit 0
Read:
0000
IRQF
IMASK
MODE
Write:
ACK
Reset:
00000000
= Unimplemented
Figure 8-4. IRQ Status and Control Register (INTSCR)
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