参数资料
型号: MC92604VM
厂商: Freescale Semiconductor
文件页数: 10/16页
文件大小: 0K
描述: IC ETH TXRX DUAL GIG 196-MAPBGA
标准包装: 630
类型: 收发器
驱动器/接收器数: 2/2
规程: 千兆位以太网
电源电压: 4.5 V ~ 5.5 V
安装类型: 表面贴装
封装/外壳: 196-LBGA
供应商设备封装: 196-MAPBGA(15x15)
包装: 托盘
MOTOROLA
MC92603 Quad and MC92604 Dual Gigabit Ethernet Transceivers
3
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Block Diagram
The MC92603 is a highly integrated device containing all of the logic needed to facilitate the application
and test of a high-speed serial interface. No external components, other than the normal power supply
decoupling network are required. A block diagram of the MC92603 GEt device is shown in Figure 1.
Figure 1. MC9603 Block Diagram
The MC92603 and MC92604 perform the Physical Coding Sublayer (PCS) and the Physical Medium
Attachment (PMA) sublayer for 1000BASE-X PHY as dened in clause 36 of the IEEE 802.3-2002
specication.
Figure 2 shows a typical application for the MC92603. It may be used as a Quad 1000BASE-X PHY or is
backplane applications. On high density line cards with a large number of Gig Ethernet ports it is desirable
to use the RGMII interfaces to reduce the number of signal traces on the PCB.
The MC92603 and MC92604 may be used to interface directly to the gigabit MACs integrated into the MPC
PowerQUICC III communications processors. They are also interface compatible to the C-Port, C-3, and
C-5 network processors available from Motorola.
XMIT_x_ENABLE
XMIT_x_[7:0]
XMIT_x_K/ERR
XMIT_x_CLK
RECV_x_[7:0]
RECV_x_CLK
RECV_x_K
RECV_x_ERR
RECV_x_DV
RLINK_x_P
RLINK_x_N
RESET
REF_CLK
GTX_CLK125_[1:0]
MD_DATA
MD_CLK
MD_ADR[4:2]
CONFIG_INPUTS
TDI,TRST,TCK
TDO
XCVR_x_DISABLE
XCVR_x_LBE
MEDIA
MD_ENABLE
Four Transceivers x = A, B, C, D
XLINK_x_N
XLINK_x_P
BIST
8B/10B
Encoder
8B/10B
Decoder
6
2
3
TTL_REF_CLK
Clock
Generator
Receiv
er
Interf
ace
System
PLL
Link Controller
MDIO
Controller
JTAG
Controller
T
ransmitter
Receiv
er
FIFO
F
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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