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| 型号： | MC92604VM |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 2/16页 |
| 文件大小： | 0K |
| 描述： | IC ETH TXRX DUAL GIG 196-MAPBGA |
| 标准包装： | 630 |
| 类型： | 收发器 |
| 驱动器/接收器数： | 2/2 |
| 规程： | 千兆位以太网 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 196-LBGA |
| 供应商设备封装： | 196-MAPBGA（15x15） |
| 包装： | 托盘 |
10
MC92603 Quad and MC92604 Dual Gigabit Ethernet Transceivers
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Data Alignment Congurations
Non-Aligned Mode (BSYNC = low)
In this mode no attempt is made to align the incoming data stream. The bits are simply accumulated into
10-bit code groups and forwarded. This mode should be used only with Backplane 10-/5-bit Data Mode
(TBIE=high, COMPAT=low), and with Word Synchronization disabled (WSYNC1 & WSYNC0=low).
Byte-Aligned Mode (BSYNC = high)
The remaining 4 receiver operating modes align the incoming serial data into 10 bit code groups. At
power-up, the receiver starts an alignment procedure, searching for the 8-bit pattern dened by the 8B/10B
COMMA codes. Synchronization logic checks for the distinct sequence, ‘00111110xx’ and ‘11000001xx’
(ordered bit 0 to bit 7), characteristic of the three valid COMMA code groups. The search is done on the
10-bit data in the receiver, and is therefore independent of the state of TBIE or COMPAT. Alignment
requires a minimum of four, error-free, received COMMA code groups to ensure proper alignment and lock.
Non-COMMA code groups may be interspersed with the COMMA code groups. The disparity of the
COMMA code groups is not important to alignment and can be positive, negative or any combination. The
receiver begins to forward received code groups once locked on an alignment.
Word Synchronization
When the MC92603 is congured in either of the ‘aligned backplane’ modes (BSYNC high and COMPAT
low), the four receivers can be used cooperatively to receive 32-bit (40-bit if TBIE is high) aligned word
transfers. Word alignment is enabled by setting the word synchronization enable inputs, WSYNC1 or
WSYNC0, high.
The word synchronization aligns code groups in the receiver’s alignment FIFO. Synchronization is
accomplished by lining up word synchronization events detected by each of the receivers, such that all are
coincident at the same output stage of their FIFO.
Word synchronization events must be received at all concerned receivers within 40 bit-times of each other.
There are three word synchronization events as dened in Table 6.
Table 5. Receiver Errors Reported for Receiver Modes
Description of Reported Errors
GMII/
RGMII
TBI/
RTBI
8-bit/
4-bit
10-bit/
5bit
Disparity Error: The 8B/10B decoder detected a disparity error.
YES
NO
Code Error: The 8B/10B decoder detected an illegal code group.
YES
NO
YES
NO
Overrun
YES
Underrun
YES
Not Word Sync: The receiver is byte synchronized but has not achieved or
has lost word alignment and is searching for alignment.
NO
YES
Not Byte Sync: The receiver is in start-up or has lost byte alignment and
is searching for alignment.
YES
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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| MC92604ZT | 功能描述:IC TXRX ETH DUAL GIG 196-MAPBGA RoHS:否 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:25 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:4.5 V ~ 5.5 V 安装类型:通孔 封装/外壳:16-DIP（0.300"，7.62mm） 供应商设备封装:16-PDIP 包装:管件 |
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