参数资料
型号: MC9328MX1DVM15R2
厂商: Freescale Semiconductor
文件页数: 25/100页
文件大小: 0K
描述: IC MCU I.MX 150MHZ 256-MAPBGA
标准包装: 1,000
系列: i.MX1
核心处理器: ARM9
芯体尺寸: 32-位
速度: 150MHz
连通性: EBI/EMI,I²C,MMC,智能卡,SPI,SSI,UART/USART,USB
外围设备: DMA,I²S,LCD,POR,PWM,WDT
输入/输出数: 110
程序存储器类型: ROMless
电压 - 电源 (Vcc/Vdd): 1.7 V ~ 3.3 V
振荡器型: 外部
工作温度: -30°C ~ 70°C
封装/外壳: 256-MAPBGA
包装: 带卷 (TR)
Functional Description and Application Information
MC9328MX1 Technical Data, Rev. 7
30
Freescale Semiconductor
4.4.1
DTACK Signal Description
The DTACK signal is the external input data acknowledge signal. When using the external DTACK signal
as a data acknowledge signal, the bus time-out monitor generates a bus error when a bus cycle is not
terminated by the external DTACK signal after 1022 HCLK counts have elapsed. Only the CS5 group
supports DTACK signal function when the external DTACK signal is used for data acknowledgement.
4.4.2
DTACK Signal Timing
Figure 6 through Figure 9 show the access cycle timing used by chip-select 5. The signal values and units
of measure for this figure are found in the associated tables.
4a
Clock1 rise to Output Enable Valid
2.32
2.62
6.85
2.3
2.6
6.8
ns
4b
Clock1 rise to Output Enable Invalid
2.11
2.52
6.55
2.1
2.5
6.5
ns
4c
Clock1 fall to Output Enable Valid
2.38
2.69
7.04
2.3
2.6
6.8
ns
4d
Clock1 fall to Output Enable Invalid
2.17
2.59
6.73
2.1
2.5
6.5
ns
5a
Clock1 rise to Enable Bytes Valid
1.91
2.52
5.54
1.9
2.5
5.5
ns
5b
Clock1 rise to Enable Bytes Invalid
1.81
2.42
5.24
1.8
2.4
5.2
ns
5c
Clock1 fall to Enable Bytes Valid
1.97
2.59
5.69
1.9
2.5
5.5
ns
5d
Clock1 fall to Enable Bytes Invalid
1.76
2.48
5.38
1.7
2.4
5.2
ns
6a
Clock1 fall to Load Burst Address Valid
2.07
2.79
6.73
2.0
2.7
6.5
ns
6b
Clock1 fall to Load Burst Address Invalid
1.97
2.79
6.83
1.9
2.7
6.6
ns
6c
Clock1 rise to Load Burst Address Invalid
1.91
2.62
6.45
1.9
2.6
6.4
ns
7a
Clock1 rise to Burst Clock rise
1.61
2.62
5.64
1.6
2.6
5.6
ns
7b
Clock1rise to Burst Clock fall
1.61
2.62
5.84
1.6
2.6
5.8
ns
7c
Clock1 fall to Burst Clock rise
1.55
2.48
5.59
1.5
2.4
5.4
ns
7d
Clock1 fall to Burst Clock fall
1.55
2.59
5.80
1.5
2.5
5.6
ns
8a
Read Data setup time
5.54
5.5
ns
8b
Read Data hold time
0
0
ns
9a
Clock1 rise to Write Data Valid
1.81
2.72
6.85
1.8
2.7
6.8
ns
9b
Clock1 fall to Write Data Invalid
1.45
2.48
5.69
1.4
2.4
5.5
ns
9c
Clock1 rise to Write Data Invalid
1.63
1.62
ns
10a
DTACK setup time
2.52
2.5
ns
1 Clock refers to the system clock signal, HCLK, generated from the System DPLL
Table 12. EIM Bus Timing Parameter Table (Continued)
Ref No.
Parameter
1.8 ± 0.1 V
3.0 ± 0.3 V
Unit
Min
Typical
Max
Min
Typical
Max
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