参数资料
型号: MC9328MX1DVM15R2
厂商: Freescale Semiconductor
文件页数: 67/100页
文件大小: 0K
描述: IC MCU I.MX 150MHZ 256-MAPBGA
标准包装: 1,000
系列: i.MX1
核心处理器: ARM9
芯体尺寸: 32-位
速度: 150MHz
连通性: EBI/EMI,I²C,MMC,智能卡,SPI,SSI,UART/USART,USB
外围设备: DMA,I²S,LCD,POR,PWM,WDT
输入/输出数: 110
程序存储器类型: ROMless
电压 - 电源 (Vcc/Vdd): 1.7 V ~ 3.3 V
振荡器型: 外部
工作温度: -30°C ~ 70°C
封装/外壳: 256-MAPBGA
包装: 带卷 (TR)
Functional Description and Application Information
MC9328MX1 Technical Data, Rev. 7
Freescale Semiconductor
69
4.10.1
Command Response Timing on MMC/SD Bus
The card identification and card operation conditions timing are processed in open-drain mode. The card
response to the host command starts after exactly NID clock cycles. For the card address assignment,
SET_RCA is also processed in the open-drain mode. The minimum delay between the host command and
card response is NCR clock cycles as illustrated in Figure 48. The symbols for Figure 48 through
Figure 52 are defined in Table 29.
Table 28. SDHC Bus Timing Parameter Table
Ref
No.
Parameter
1.8 ± 0.1 V
3.0 ± 0.3 V
Unit
Minimum
Maximum
Minimum
Maximum
1
CLK frequency at Data transfer Mode
(PP)1—10/30 cards
1 C
L 100 pF / 250 pF (10/30 cards)
0
25/5
0
25/5
MHz
2
CLK frequency at Identification Mode2
2 C
L 250 pF (21 cards)
0
400
0
400
kHz
3a
Clock high time1—10/30 cards
6/33
10/50
ns
3b
Clock low time1—10/30 cards
15/75
10/50
ns
4a
Clock fall time1—10/30 cards
10/50
(5.00)3
10/50
ns
4b
Clock rise time1—10/30 cards
14/67
(6.67)3
10/50
ns
5a
Input hold time3—10/30 cards
3 C
L 25 pF (1 card)
10.3/10.3
9/9
ns
5b
Input setup time3—10/30 cards
10.3/10.3
9/9
ns
6a
Output hold time3—10/30 cards
5.7/5.7
5/5
ns
6b
Output setup time3—10/30 cards
5.7/5.7
5/5
ns
7
Output delay time3
0
16
0
14
ns
Table 29. State Signal Parameters for Figure 48 through Figure 52
Card Active
Host Active
Symbol
Definition
Symbol
Definition
Z
High impedance state
S
Start bit (0)
D
Data bits
T
Transmitter bit (Host = 1, Card = 0)
*
Repetition
P
One-cycle pull-up (1)
CRC
Cyclic redundancy check bits (7 bits)
E
End bit (1)
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