参数资料
型号: MC9328MX1VH20
厂商: MOTOROLA INC
元件分类: 微控制器/微处理器
英文描述: 200 MHz, RISC PROCESSOR, PBGA256
封装: 14 X 14 MM, 1.30 MM HEIGHT, 0.80 MM PITCH, MAPBGA-256
文件页数: 56/86页
文件大小: 1465K
代理商: MC9328MX1VH20
6
MC9328MX1 Advance Information
MOTOROLA
Signals and Connections
EXTAL32K
32 KHz crystal input
XTAL32K
32 KHz crystal output
CLKO
Clock Out signal selected from internal clock signals.
RESET_IN
Master Reset—External active low Schmitt trigger input signal. When this signal goes
active, all modules (except the reset module and the clock control module) are reset.
RESET_OUT
Reset Out—Internal active low output signal from the Watchdog Timer module and is
asserted from the following sources: Power-on reset, External reset (RESET_IN), and
Watchdog time-out.
POR
Power On Reset—Internal active high Schmitt trigger input signal. The POR signal is
normally generated by an external RC circuit designed to detect a power-up event.
JTAG
TRST
Test Reset Pin—External active low signal used to asynchronously initialize the JTAG
controller.
TDO
Serial Output for test instructions and data. Changes on the falling edge of TCK.
TDI
Serial Input for test instructions and data. Sampled on the rising edge of TCK.
TCK
Test Clock to synchronize test logic and control register access through the JTAG port.
TMS
Test Mode Select to sequence the JTAG test controller’s state machine. Sampled on the
rising edge of TCK.
DMA
BIG_ENDIAN
Big Endian—Input signal that determines the configuration of the external chip-select
space. If it is driven logic-high at reset, the external chip-select space will be configured to
little endian. If it is driven logic-low at reset, the external chip-select space will be
configured to big endian.
ETM
ETMTRACESYNC
ETM sync signal which is multiplexed with A24. ETMTRACESYNC is selected in ETM
mode.
ETMTRACECLK
ETM clock signal which is multiplexed with A23. ETMTRACECLK is selected in ETM
mode.
ETMPIPESTAT [2:0]
ETM status signals which are multiplexed with A [22:20]. ETMPIPESTAT [2:0] are
selected in ETM mode.
ETMTRACEPKT [7:0]
ETM packet signals which are multiplexed with ECB, LBA, BCLK, PA17, A [19:16].
ETMTRACEPKT [7:0] are selected in ETM mode.
CMOS Sensor Interface
CSI_D [7:0]
Sensor port data
CSI_MCLK
Sensor port master clock
Table 2. MC9328MX1 Signal Descriptions (Continued)
Signal Name
Function/Notes
相关PDF资料
PDF描述
MC9328MX1VH15 150 MHz, MICROPROCESSOR, PBGA256
MC9328MX1VM15 32-BIT, 150 MHz, RISC PROCESSOR, PBGA256
MC9328MX1CVM15R2 32-BIT, 150 MHz, RISC PROCESSOR, PBGA256
MC9328MX1VM20R2 32-BIT, 200 MHz, RISC PROCESSOR, PBGA256
MC9328MX1CVM15 32-BIT, 150 MHz, RISC PROCESSOR, PBGA256
相关代理商/技术参数
参数描述
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