参数资料
型号: MC9328MXSCVF10
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 100 MHz, MICROPROCESSOR, PBGA225
封装: 13 X 13 MM, PLASTIC, BGA-225
文件页数: 11/72页
文件大小: 1411K
代理商: MC9328MXSCVF10
Specifications
MC9328MXS Advance Information, Rev. 0
Freescale Semiconductor
19
3.9.2.1 DTACK Read Cycle without DMA
Figure 6. DTACK Read Cycle without DMA
Table 13. Read Cycle without DMA: WSC = 111111, DTACK_SEL=0, HCLK=96MHz
Number
Characteristic
3.0 ± 0.3 V
Unit
Minimum
Maximum
1
OE and EB assertion time
See note 3
ns
2
CS5 pulse width
3T
ns
3
OE negated to address inactive
46.39
ns
4
DTACK asserted after CS5 asserted
1019T
ns
5
DTACK asserted to OE negated
3T+1.83
4T+6.6
ns
6
Data hold timing after OE negated
0–
ns
7
Data ready after DTACK asserted
0T
ns
8
OE negated to CS negated
0.5T-0.68
0.5T-0.06
ns
9
OE negated after EB negated
0.06
0.18
ns
10
DTACK pulse width
1T
3T
ns
Note:
1. DTACK asserted means DTACK becomes low level.
2. T is the system clock period. (For 96 MHz system clock, T=10.42 ns)
3. OE and EB assertion time is programmable by OEA bit in CS5L register. EB assertion in read cycle will occur only when
EBC bit in CS5L register is clear.
4. Address becomes valid and CS asserts at the start of read access cycle.
5. The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state.
DTACK
Address
EB
CS5
OE
programmable
min 0ns
3
2
9
(input to i.MX)
5
1
4
6
10
7
DATABUS
8
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