参数资料
型号: MC9328MXSCVF10
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 100 MHz, MICROPROCESSOR, PBGA225
封装: 13 X 13 MM, PLASTIC, BGA-225
文件页数: 16/72页
文件大小: 1411K
代理商: MC9328MXSCVF10
Specifications
MC9328MXS Advance Information, Rev. 0
Freescale Semiconductor
23
3.9.2.5 WAIT Read Cycle without DMA
Figure 10. WAIT Read Cycle without DMA
Table 17. WAIT Read Cycle without DMA: WSC = 111111, DTACK_SEL=1, HCLK=96MHz
Number
Characteristic
3.0 ± 0.3 V
Unit
Minimum
Maximum
1OE and EB assertion time
See note 2
ns
2CS5 pulse width
3T
ns
3OE negated to address inactive
56.81
57.28
ns
4
Wait asserted after OE asserted
1020T
ns
5
Wait asserted to OE negated
2T+1.57
3T+7.33
ns
6
Data hold timing after OE negated
T-1.49
ns
7
Data ready after wait asserted
0
T
ns
8
OE negated to CS negated
1.5T-0.68
1.5T-0.06
ns
9
OE negated after EB negated
0.06
0.18
ns
10
Become low after CS5 asserted
0
1019T
ns
11
Wait pulse width
1T
1020T
ns
Note:
1. T is the system clock period. (For 96 MHz system clock, T=10.42 ns)
2. OE and EB assertion time is programmable by OEA bit in CS5L register. EB assertion in read cycle will occur only when
EBC bit in CS5L register is clear.
3. Address becomes valid and CS asserts at the start of read access cycle.
4. The external wait input requirement is eliminated when CS5 is programmed to use internal wait state.
WAIT
Address
EB
CS5
OE
DATABUS
programmable
min 0ns
1
2
3
8
9
5
6
7
11
10
4
(input to i.MX)
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