- 您现在的位置：买卖IC网 > PDF目录11663 > MC9RS08KA2CDB (Freescale Semiconductor)IC MCU 8-BIT 2K FLASH 6-DFN PDF资料下载
参数资料
| 型号： | MC9RS08KA2CDB |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 7/136页 |
| 文件大小： | 0K |
| 描述： | IC MCU 8-BIT 2K FLASH 6-DFN |
| 产品培训模块： | Mechatronics USBSpyder08 Discovery Kit RS08KA2 Low-End Microcontroller Series MC9RS08KA8 Microcontroller |
| 标准包装： | 490 |
| 系列： | RS08 |
| 核心处理器： | RS08 |
| 芯体尺寸： | 8-位 |
| 速度： | 10MHz |
| 外围设备： | LVD，POR，WDT |
| 输入/输出数： | 2 |
| 程序存储器容量： | 2KB（2K x 8） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 63 x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 1.8 V ~ 5.5 V |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 6-VDFN 裸露焊盘 |
| 包装： | 托盘 |
| 产品目录页面： | 726 (CN2011-ZH PDF) |
| 配用： | DEMO9RS08KA2-ND - DEMO BOARD FOR 9RS08KA2 |
第1页第2页第3页第4页第5页第6页当前第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页
Chapter 12 Development Support
MC9RS08KA2 Series Data Sheet, Rev. 4
104
Freescale Semiconductor
12.4.2
BDC Breakpoint Match Register
This 16-bit register holds the 14-bit address for the hardware breakpoint in the BDC. The BKPTEN and
FTS control bits in BDCSCR are used to enable and configure the breakpoint logic. Dedicated serial BDC
commands (READ_BKPT and WRITE_BKPT) are used to read and write the BDCBKPT register.
Breakpoints are normally set while the target MCU is in active background mode before running the user
application program. However, because READ_BKPT and WRITE_BKPT are non-intrusive commands,
they could be executed even while the user program is running. For additional information about setup and
use of the hardware breakpoint logic in the BDC, refer to the RS08 Family Reference Manual.”
5
BKPTEN
BDC Breakpoint Enable — If this bit is clear, the BDC breakpoint is disabled and the FTS (force tag select)
control bit and BDCBKPT match register are ignored
0 BDC breakpoint disabled.
1 BDC breakpoint enabled.
4
FTS
Force/Tag Select — When FTS = 1, a breakpoint is requested whenever the CPU address bus matches the
BDCBKPT match register
. When FTS = 0, a match between the CPU address bus and the BDCBKPT register
causes the fetched opcode to be tagged
. If this tagged opcode ever reaches the end of the instruction queue,
the CPU enters active background mode rather than executing the tagged opcode
.
0 Tag opcode at breakpoint address and enter active background mode if CPU attempts to execute that
instruction.
1 Breakpoint match forces active background mode at next instruction boundary (address need not be an
opcode).
2
WS
Wait or Stop Status — When the target CPU is in wait or stop mode, most BDC commands cannot function
.
However, the BACKGROUND command can be used to force the target CPU out of wait or stop and into active
background mode where all BDC commands work
. Whenever the host forces the target MCU into active
background mode, the host must issue a READ_STATUS command to check that BDMACT = 1 before
attempting other BDC commands
.
0 Target CPU is running user application code or in active background mode (was not in wait or stop mode when
background became active).
1 Target CPU is in wait or stop mode, or a BACKGROUND command was used to change from wait or stop to
active background mode.
1
WSF
Wait or Stop Failure Status — This status bit is set if a memory access command failed due to the target CPU
executing a wait or stop instruction at or about the same time
. The usual recovery strategy is to issue a
BACKGROUND command to get out of wait or stop mode into active background mode, repeat the command
that failed, then return to the user program
. (Typically, the host would restore CPU registers and stack values and
re-execute the wait or stop instruction
.)
0 Memory access did not conflict with a wait or stop instruction.
1 Memory access command failed because the CPU entered wait or stop mode.
Table 12-1. BDCSCR Register Field Descriptions (continued)
Field
Description
相关PDF资料 |
PDF描述 |
|---|---|
| RE46C107S16F | IC HORN DRIVER DUAL 16SOIC |
| RE46C117E8F | IC HORN DRIVER DUAL 8PDIP |
| MC9S08SF4MTJ | MCU 8BIT 4K FLASH 20-TSSOP |
| MC9S08QE4CWJ | IC MCU 8BIT 4K FLASH 20-SOIC |
| MC9S08SH4CWJ | MCU 8BIT 4K FLASH 20-SOIC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MC9RS08KA2CPC | 功能描述:8位微控制器 -MCU 2K FLASH W/ ACMP 62 RAM RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| MC9RS08KA2CSC | 功能描述:8位微控制器 -MCU 2K FLASH W/ ACMP 62 RAM RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| MC9RS08KA2CSCR | 功能描述:8位微控制器 -MCU 2K FLASH W/ ACMP 62 RAM RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| MC9RS08KA2DB | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Microcontrollers |
| MC9RS08KA2PC | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Microcontrollers |
发布紧急采购，3分钟左右您将得到回复。