参数资料
型号: MCF53017CMJ240J
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: MICROPROCESSOR, PBGA256
封装: 17 X 17 MM, ROHS COMPLIANT, PLASTIC, MAPBGA-256
文件页数: 19/62页
文件大小: 2365K
代理商: MCF53017CMJ240J
MCF5301x Data Sheet, Rev. 5
Preliminary—Subject to Change Without Notice
Preliminary Electrical Characteristics
Freescale Semiconductor
26
Chip-select, FB_CS0 can be dedicated to boot ROM access and can be programmed to be byte (8 bits), word (16 bits), or
longword (32 bits) wide. Control signal timing is 1‘compatible with common ROM/flash memories.
5.6.1.1
FlexBus AC Timing Characteristics
The following timing numbers indicate when data will be latched or driven onto the external bus, relative to the system clock.
NOTE
The processor drives the data lines during the first clock cycle of the transfer with the full
32-bit address. This may be ignored by standard connected devices using non-multiplexed
address and data buses. However, some applications may find this feature beneficial.
The address and data busses are muxed between the FlexBus and SDRAM controller. At
the end of the read and write bus cycles the address signals are indeterminate.
Table 12. FlexBus AC Timing Specifications
Num
Characteristic
Symbol
Min
Max
Unit
Notes
Frequency of Operation
80
Mhz
fsys/3
FB1
Clock Period (FB_CLK)
tFBCK
12.5
ns
tcyc
FB2
Address, Data, and Control Output Valid (A[23:0], D[31:0],
FB_CS[5:0], R/W, TS, BE/BWE[3:0] and OE)
tFBCHDCV
—7.0
ns
1
Timing for chip selects only applies to the FB_CS[5:0] signals. Please see Section 5.7.2, “DDR SDRAM AC Timing
Characteristics” for SD_CS[3:0] timing.
FB3
Address, Data, and Control Output Hold (A[23:0], D[31:0],
FB_CS[5:0], R/W, TS, BE/BWE[3:0], and OE)
tFBCHDCI
1—
ns
1, 2
2
The FlexBus supports programming an extension of the address hold. Please consult the MCF5301x Reference
Manual for more information.
FB4
Data Input Setup
tDVFBCH
3.5
ns
FB5
Data Input Hold
tDIFBCH
0—
ns
FB6
Transfer Acknowledge (TA) Input Setup
tCVFBCH
4—
ns
FB7
Transfer Acknowledge (TA) Input Hold
tCIFBCH
0—
ns
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