参数资料
型号: MCHC11F1CFNE2R
厂商: Freescale Semiconductor
文件页数: 28/158页
文件大小: 0K
描述: MCU 8BIT 1KRAM 512EE 68-PLCC
标准包装: 250
系列: HC11
核心处理器: HC11
芯体尺寸: 8-位
速度: 2MHz
连通性: SCI,SPI
外围设备: POR,WDT
输入/输出数: 30
程序存储器类型: ROMless
EEPROM 大小: 512 x 8
RAM 容量: 1K x 8
电压 - 电源 (Vcc/Vdd): 4.75 V ~ 5.25 V
数据转换器: A/D 8x8b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 68-LCC(J 形引线)
包装: 带卷 (TR)
TIMING SYSTEM
TECHNICAL DATA
9-17
Bit 7 — Not implemented
Always reads zero
PAEN — Pulse Accumulator System Enable
0 = Pulse accumulator disabled
1 = Pulse accumulator enabled
PAMOD — Pulse Accumulator Mode
0 = Event counter
1 = Gated time accumulation
PEDGE — Pulse Accumulator Edge Control
This bit has different meanings depending on the state of the PAMOD bit, as shown in
Bit 3 — Not implemented
Always reads zero
I4/O5 — Input Capture 4/Output Compare 5
0 = Output compare 5 function enable (No IC4)
1 = Input capture 4 function enable (No OC5)
RTR[1:0] — RTI Interrupt Rate Selects
9.6.2 Pulse Accumulator Count Register
This 8-bit read/write register contains the count of external input events at the PAI in-
put, or the accumulated count. The PACNT is readable even if PAI is not active in gat-
ed time accumulation mode. The counter is not affected by reset and can be read or
written at any time. Counting is synchronized to the internal PH2 clock so that incre-
menting and reading occur during opposite half cycles.
PACTL — Pulse Accumulator Control
$1026
Bit 7
654321
Bit 0
PAEN
PAMOD
PEDGE
I4/O5
RTR1
RTR0
RESET:
0000000
0
Table 9-6 Pulse Accumulator Edge Detection Control
PAMOD
PEDGE
Action on Clock
0
PAI falling edge increments the counter.
0
1
PAI rising edge increments the counter.
1
0
A zero on PAI inhibits counting.
1
A one on PAI inhibits counting.
PACNT — Pulse Accumulator Count
$1027
Bit 7
654321
Bit 0
Bit 7
654321
Bit 0
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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