参数资料
型号: MCHC11F1CFNE2R
厂商: Freescale Semiconductor
文件页数: 74/158页
文件大小: 0K
描述: MCU 8BIT 1KRAM 512EE 68-PLCC
标准包装: 250
系列: HC11
核心处理器: HC11
芯体尺寸: 8-位
速度: 2MHz
连通性: SCI,SPI
外围设备: POR,WDT
输入/输出数: 30
程序存储器类型: ROMless
EEPROM 大小: 512 x 8
RAM 容量: 1K x 8
电压 - 电源 (Vcc/Vdd): 4.75 V ~ 5.25 V
数据转换器: A/D 8x8b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 68-LCC(J 形引线)
包装: 带卷 (TR)
PIN DESCRIPTIONS
MC68HC11F1
2-8
TECHNICAL DATA
2.11.2 Port B
Port B is an 8-bit output-only port. In single-chip modes, port B pins are general-pur-
pose output pins (PB[7:0]). In expanded modes, port B pins act as the high-order ad-
dress lines (ADDR[15:8]) of the address bus.
PORTB can be read at any time. Reads of PORTB return the pin driver input level. If
PORTB is written, the data is stored in internal latches. It drives the pins only in single-
chip or bootstrap mode. In expanded operating modes, port B pins are the high-order
address outputs (ADDR[15:8]).
2.11.3 Port C
Port C is an 8-bit general-purpose I/O port with a data register (PORTC) and a data
direction register (DDRC). In single-chip modes, port C pins are general-purpose I/O
pins (PC[7:0]). In expanded modes, port C pins are configured as data bus pins (DA-
TA[7:0]).
PORTC can be read at any time. Inputs return the pin level; outputs return the pin driv-
er input level. If PORTC is written, the data is stored in internal latches. It drives the
pins only if they are configured as outputs in single-chip or bootstrap mode. Port C pins
are general-purpose inputs out of reset in single-chip and bootstrap modes. In expand-
ed and test modes, these pins are data bus lines out of reset.
The CWOM control bit in the OPT2 register disables port C’s P-channel output drivers.
Because the N-channel driver is not affected by CWOM, setting CWOM causes port
C to become an open-drain-type output port suitable for wired-OR operation. In wired-
OR mode, (PORTC bits are at logic level zero), pins are actively driven low by the N-
channel driver. When a port C bit is at logic level one, the associated pin is in a high-
impedance state, as neither the N-channel nor the P-channel devices are active. It is
customary to have an external pull-up resistor on lines that are driven by open-drain
devices. Port C can only be configured for wired-OR operation when the MCU is in sin-
gle-chip or bootstrap modes.
2.11.4 Port D
Port D, a 6-bit general-purpose I/O port, has a data register (PORTD) and a data di-
rection register (DDRD). The six port D lines (D[5:0]) can be used for general-purpose
I/O, for the serial communications interface (SCI) and serial peripheral interface (SPI)
subsystems.
PORTD can be read at any time. Inputs return the pin level; outputs return the pin driv-
er input level. If PORTD is written, the data is stored in internal latches and can be driv-
en only if port D is configured for general-purpose output.
The DWOM control bit in the SPCR register disables port D’s P-channel output drivers.
Because the N-channel driver is not affected by DWOM, setting DWOM causes port
D to become an open-drain-type output port suitable for wired-OR operation. In wired-
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