参数资料
型号: MCIMX351AVM4BR2
厂商: Freescale Semiconductor
文件页数: 116/147页
文件大小: 0K
描述: IC MPU I.MX35 400MAPBGA
标准包装: 1,000
系列: i.MX35
核心处理器: ARM11
芯体尺寸: 32-位
速度: 400MHz
连通性: 1 线,CAN,EBI/EMI,以太网,I²C,MMC,SPI,SSI,UART/USART,USB OTG
外围设备: DMA,I²S,LCD,POR,PWM,WDT
输入/输出数: 96
程序存储器类型: ROMless
RAM 容量: 128K x 8
电压 - 电源 (Vcc/Vdd): 1.22 V ~ 1.47 V
振荡器型: 外部
工作温度: -40°C ~ 85°C
封装/外壳: 400-LFBGA
包装: 带卷 (TR)
i.MX35 Applications Processors for Automotive Products, Rev. 10
Freescale Semiconductor
70
4.9.13.1
Synchronous Interfaces
This section discusses the interfaces to active matrix TFT LCD panels, Sharp HR-TFT, and dual-port smart
displays.
4.9.13.1.4
Interface to Active Matrix TFT LCD Panels, Functional Description
Figure 47 depicts the LCD interface timing for a generic active matrix color TFT panel. In this figure,
signals are shown with negative polarity. The sequence of events for active matrix interface timing is as
follows:
DISPB_D3_CLK latches data into the panel on its negative edge (when positive polarity is
selected). In active mode, DISPB_D3_CLK runs continuously.
DISPB_D3_HSYNC causes the panel to start a new line.
DISPB_D3_VSYNC causes the panel to start a new frame. It always encompasses at least one
HSYNC pulse.
DISPB_D3_DRDY acts like an output enable signal to the CRT display. This output enables the
data to be shifted to the display. When disabled, the data is invalid and the trace is off.
Figure 47. Interface Timing Diagram for TFT (Active Matrix) Panels
4.9.13.1.5
Interface to Active Matrix TFT LCD Panels, Electrical Characteristics
Figure 48 depicts the horizontal timing (timing of one line), including both the horizontal sync pulse and
the data. All figure parameters shown are programmable. The timing images correspond to inverse polarity
DISPB_D3_CLK
12
3
m
m–1
DISPB_D3_HSYNC
DISPB_D3_VSYNC
DISPB_D3_HSYNC
LINE 1
LINE 2
LINE 3
LINE 4
LINE n – 1
LINE n
DISPB_D3_DRDY
DISPB_D3_DATA
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