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参数资料
型号： MCIMX537CVV8C
厂商： FREESCALE SEMICONDUCTOR INC
元件分类： 微控制器/微处理器
英文描述： 32-BIT, 800 MHz, RISC PROCESSOR, PBGA529
封装： 19 X 19 MM, 0.80 MM PITCH, ROHS COMPLIANT, PLASTIC, TEPBGA-529
文件页数： 119/172页
文件大小： 4562K
代理商： MCIMX537CVV8C
i.MX53 Applications Processors for Industrial Products, Rev. 3
50
Freescale Semiconductor
Electrical Characteristics
Table 35. NFC—Timing Characteristics
ID
Parameter
Symbol
Asymmetric Mode Min
Symmetric Mode
Min
Max
NF1
NFCLE setup Time
tCLS
2T + 0.1
—
NF2
NFCLE Hold Time
tCLH
T – 4.45
—
NF31
1 In case of NUM_OF_DEVICES is greater than 0 (for example, interleaved mode), then only during the data phase of
symmetric mode the setup time will equal 1.5T + 0.95.
NFCE_B Setup Time
tCS
3T + 0.95
3T+0.95
—
NF4
NFCE_B Hold Time
tCH
2T–5.55
1.5T–5.55
—
NF5
NFWE_B Pulse Width
tWP
T–1.4
0.5T – 1.4
—
NF6
NFALE Setup Time
tALS
2T + 0.1
—
NF7
NFALE Hold Time
tALH
T – 4.45
—
NF8
Data Setup Time
tDS
T–0.9
0.5T – 0.9
—
NF9
Data Hold Time
tDH
T – 5.55
0.5T – 5.55
—
NF10
Write Cycle Time
tWC
2T
T–0.5
—
NF11
NFWE_B Hold Time
tWH
T – 1.15
0.5T – 1.15
—
NF12
Ready to NFRE_B Low
tRR
9T + 8.9
—
NF13
NFRE_B Pulse Width
tRP
1.5T
0.5T–1
—
NF14
READ Cycle Time
tRC
2T
T
—
NF15
NFRE_B High Hold Time
tREH
0.5T – 1.15
—
NF162
2 tDSR is calculated by the following formula:
Asymmetric mode:
tDSR = tREpd + tDpd + 1/
2T – Tdl
2
Symmetric mode:
tDSR = tREpd + tDpd – Tdl2
tREpd + tDpd = 11.2 ns (including clock skew)
where tREpd is RE propogation delay in the chip including I/O pad delay, and tDpd is Data propogation delay from I/O pad to
EXTMC including I/O pad delay.
tDSR can be used to determine tREA max parameter with the following formula: tREA = 1.5T – tDSR.
Data Setup on READ
tDSR
11.2 + 0.5T – Tdl3
3 Tdl is composed of 4 delay-line units each generates an equal delay with min 1.25 ns and max 1 aclk period (Taclk). Default
is 1/4 aclk period for each delay-line unit, so all 4 delay lines together generates a total of 1 aclk period. Taclk is
“emi_slow_clk” of the system, which default value is 7.5 ns (133 MHz).
11.2 – Tdl2
—
NF174
Data Hold on READ
tDHR
0—
2Taclk +T
NF185
Data Hold on READ
tDHR
—Tdl2 –11.2
2Taclk +T
NF19
CLE to RE delay
tCLR
9T
—
NF20
CE to RE delay
tCRE
T–3.45
T+0.3
NF21
WE high to RE low
tWHR
10.5T
—
NF22
WE high to busy
tWB
——
6T
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相关代理商/技术参数
参数描述
MCIMX537CVV8C 制造商:Freescale Semiconductor 功能描述:IC 32-BIT MPU 800 MHZ 529-BGA
MCIMX537CVV8CR2 功能描述:处理器 - 专门应用 iMX53 Rev 2.1 Indust RoHS:否 制造商:Freescale Semiconductor 类型:Multimedia Applications 核心:ARM Cortex A9 处理器系列:i.MX6 数据总线宽度:32 bit 最大时钟频率:1 GHz 指令/数据缓存: 数据 RAM 大小:128 KB 数据 ROM 大小: 工作电源电压: 最大工作温度:+ 95 C 安装风格:SMD/SMT 封装 / 箱体:MAPBGA-432
MCIMX538DZK1C 功能描述:处理器 - 专门应用 I.MX53 2.1 POP RoHS:否 制造商:Freescale Semiconductor 类型:Multimedia Applications 核心:ARM Cortex A9 处理器系列:i.MX6 数据总线宽度:32 bit 最大时钟频率:1 GHz 指令/数据缓存: 数据 RAM 大小:128 KB 数据 ROM 大小: 工作电源电压: 最大工作温度:+ 95 C 安装风格:SMD/SMT 封装 / 箱体:MAPBGA-432
MCIMX53EVK 制造商:Freescale Semiconductor 功能描述:
MCIMX53-LVDS 制造商:Freescale Semiconductor 功能描述:I.MX53 XGA DISPLAY LVDS DEV BOARD 制造商:Freescale Semiconductor 功能描述:I.MX53, XGA DISPLAY, LVDS, DEV BOARD 制造商:Freescale Semiconductor 功能描述:I.MX53, XGA DISPLAY, LVDS CONNECTOR, DEV BOARD; Silicon Manufacturer:Freescale; Core Architecture:ARM; Core Sub-Architecture:Cortex-A8; Silicon Core Number:i.MX5; Silicon Family Name:i.MX53
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